PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 168

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.7.3
S_ STA
Value after reset: 00
Important: This register is used only if the Layer 1 state machine of the device is disabled
(S_CONF0:L1SW = 1) and implemented in software! With the layer 1 state machine
enabled, the signals from this register are automatically evaluated.
RINF
ICV
FSYN
LD
Data Sheet
7
S_STA - S-Transceiver Status Register
Receiver INFO
00 =
01 =
10 =
11 =
Illegal Code Violation
0 =
1 =
Frame Synchronization State
0 =
1 =
Level Detection
0 =
1 =
RINF
Received INFO 0 (no signal)
Received any signal except INFO 0 or INFO 3
reserved
Received INFO 3
No illegal code violation is detected.
Illegal code violation (ANSI T1.605) in data stream is detected.
The S/T receiver is not synchronized.
The S/T receiver has synchronized to the framing bit F.
No receive signal has been detected on the line.
Any receive signal has been detected on the line.
H
0
ICV
read
154
0
FSYN
Register Description
PEF 82912/82913
Address:
0
2001-03-30
LD
0
33
H