TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 308

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

<OVVISEL>: OVV input select
<OVVMD>: OVV protection mode
<ADIN0EN>: ADC A monitor interrupt input enable
<ADIN1EN>: ADC B monitor interrupt input enable
<OVVCNT>: OVV input detection time
input to the protection circuit.
protection is enabled) by an interrupt signal from ADC A that is generated by a match between an AD
conversion result and the specified compare value.
protection is enabled) by an interrupt signal from ADC B that is generated by a match between an AD
conversion result and the specified compare value.
This bit selects whether to use port input or the monitor signal from the ADC as the OVV signal to be
This field controls the outputs of the upper and lower phases when an OVV condition occurs.
This bit selects whether to enable or disable the monitor signal input from ADC A.
This bit selects whether to enable or disable the monitor signal input from ADC B.
When the ADC monitor signal is selected, <OVVCNT> becomes invalid.
When this bit is set to enable and <OVVISEL>=1, the PMD is placed in a protection state (if OVV
When this bit is set to enable and <OVVISEL>=1, the PMD is placed in a protection state (if OVV
OVVCNT×16/fsys (resolution: 200[nsec] at 80 MHz )
0: Port input
1: ADC monitor signal
00: No output control
01: All upper phases ON, all lower phases OFF
10: All upper phases OFF, all lower phases ON
11: All phases OFF
0: Disable
1: Enable
0: Disable input
1: Enable input
1-15 (If 0 is set, it is handled as 1.)
* If OVV and EMG conditions occur simultaneously, the protection mode settings in the EMGCR
* For details, see the chapter on the ADC.
* For details, see the chapter on the ADC.
* OVVCNT is effective only when port input is selected as the OVV signal (<OVVISEL>=1).
register become effective.
* ON=High, OFF=Low [when <POLL>,<POLH>=1 (active high)]
TMPM370 16-24
Motor control circuit
TMPM370