TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 40

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

7.1.2
The following shows how an exception/interrupt is handled. In the following descriptions,
Each step is described later in this chapter.
Return from exception
Detection by CG/CPU
Handling by CPU
Handling Flowchart
Execution of ISR
Branch to ISR
Processing
indicates hardware handling.
The CG/CPU detects the exception request.
The CPU handles the exception request.
The CPU branches to the corresponding
interrupt service routine (ISR).
Necessary processing is executed。
The CPU branches to another ISR or returns
to the previous program.
TMPM370 7-2
Indicates software handling.
Description
Section 7.1.2.2
Section 7.1.2.4
Section 7.1.2.1
Section 7.1.2.3
TMPM370
See
Interrupt