TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 377

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

<ENRUN>: ENC Run
<NR1:0>: Noise Filter
<INTEN>: ENC Interrupt Enable
Internal Counter / Flag
Encoder pulse division
Rotation Direction Bit
Revolution Error flag
Noise filter counter
Encoder counter
Z Detected flag
Setting <ENRUN> to 1 and clearing <ZDET> to 0 enables the encoder operation.
There are counters and flags that are and are not cleared even if the <ENRUN> bit is cleared to 0.
The following table shows the states of the counters and flags, depending on the value of <ENRUN>.
Compare flag
The digital noise filters remove pulses narrower than the width selected by <NR1:0>.
・
In the other operating modes, <ZEN> has no effect.
0: Disabled
1: Enabled
Clearing <ENRUN> to 0 disables the encoder operation.
00: No filtering
01: Filters out pulses narrower than 31/fsys as noises.
10: Filters out pulses narrower than 63/fsys as noises.
11: Filters out pulses narrower than 127/fsys as noises.
0: Disabled
1: Enabled
<INTEN> enables and disables the ENC interrupt.
Setting <INTEN> to 1 enables interrupt generation. Clearing <INTEN> to 0 disables interrupt
generation.
<REVERR>
<ZDET>
counter
<CMP>
<UD>
cleared to 0 on the edge of ENCZ selected by <ZESEL>.
In Timer mode
<ZEN> controls whether to use the ENCZ signal as an external trigger input.
When <ZEN> = 1, the value of the encoder counter is captured into the EN0INT register and
When <ENRUN> =
(After reset)
0y0000000
0x000000
0x00
0
0
0
0
0
Set to 1 upon an error;
cleared to 0 on a read.
When <ENRUN> = 1
TMPM370 19-8
Set to 1 on detection
comparison; cleared
according to rotation
Counting down
to 0 on a read.
(During active
Set or cleared
Set to 1 upon
Counting up
operation)
direction.
Counting
of Z.
(Continues with noise
When <ENRUN> = 0
Stopped and cleared
(During idle mode)
Keeps the current
Counting up
filtering.)
Cleared
Cleared
Cleared
Cleared
value.
Encoder Input Circuit
How to clear a counter or flag
Cleared when <ENRUN> = 0.
Cleared when <ENRUN> = 0.
Cleared when <ENRUN> = 0.
Cleared when <ENRUN> = 0.
Cleared when <ENRUN> = 0.
(Write a 1 to <ENCLR>.)
Cleared only by reset.
when <ENRUN> = 0
Software clear
TMPM370