TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 437
TMPM370FYDFG
Manufacturer Part Number
TMPM370FYDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
Manufacturer
Toshiba
Datasheet
1.TMPM370FYFG.pdf
(498 pages)
Specifications of TMPM370FYDFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
QFP(14x20)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM370FYDFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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(3) Reset
(Note 1) Command sequences are executed from outside the flash memory area.
(Note 2) Each bus write cycle must be sequentially executed by 32-bit data transmit
(Note 3) For the command sequencer to recognize a command, the device must be in the
(Note 4) Upon issuing a command, if any address or data is incorrectly written, be sure to
predefined command write sequence, the flash memory will terminate the command execution
and return to the read mode.
command. While a command sequence is being executed, access to the flash
memory is prohibited. Also, don't generate any interrupt (except debug exceptions
when a Debugging probe is connected).If such an operation is made, it can result in
an unexpected read access to the flash memory and the command sequencer may
not be able to correctly recognize the command. While it could cause an abnormal
termination of the command sequence, it is also possible that the written command
is incorrectly recognized.
read mode prior to executing the command. Be sure to check before the first bus
write cycle that the FCFLCS RDY/BSY bit is set to "1." It is recommended to
subsequently execute a Read command.
perform a software reset to return to the read mode again.
A hardware reset is used to cancel the operational mode set by the command write
operation when forcibly termination during auto programming/ erasing or abnormal
termination during auto operations occurs. The flash memory has a reset input as the
memory block and it is connected to the CPU reset signal. Therefore, when the RESET
input pin of this device is set to “Low” level or when the CPU is reset due to any overflow of
the watch dog timer, the flash memory will return to the read mode terminating any
automatic operation that may be in progress. It should also be noted that applying a
hardware reset during an automatic operation can result in incorrect rewriting of data. In
such a case, be sure to perform the rewriting again.
Refer to Section 20.2.1 "Reset Operation" for CPU reset operations. After a given reset
input, the CPU will read the reset vector data from the flash memory and starts operation
after the reset is removed.
Hardware reset
TMPM370 20-45
Flash Memory Operation
TMPM370
----------------------
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