TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 92

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

This resister set the clearing standby request active level of external interrupt INT8 to INTB.
CGIMCGC
7.6.3.3
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
(Note1)
(Note2)
CG Interrupt Mode Control Register C
“0” is read
“0” is read
“0” is read
“0” is read
EMSTxx is effective only when EMCGxx is set to "100" for both rising and falling
edge. The active level used for the reset of standby can be checked by referring
EMSTxx. If interrupts are cleared with the CGICRCG register, EMSTxx is also
cleared.
Please specify the bit for the edge first and then specify the bit for the <INTxEN>.
Setting them simultaneously is prohibited.
15
23
31
7
R
R
R
R
0
0
0
0
Active state setting of INT8 standby
clear request. (101~111: setting
prohibited)
Active state setting of INT9 standby
clear request. (101~111: setting
prohibited)
Active state setting of INTA standby
clear request. (101~111: setting
prohibited)
Active state setting of INTB standby
clear request. (101~111: setting
prohibited)
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
0
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCGA2 EMCGA1 EMCGA0 EMSTA1 EMSTA0
EMCGB2 EMCGB1 EMCGB0 EMSTB1 EMSTB0
EMCG82
EMCG92
14
22
30
6
0
0
0
TMPM370 7-54
EMCG81
EMCG91
R/W
R/W
R/W
R/W
13
21
29
5
1
1
1
1
EMCG80
EMCG90
12
20
28
4
0
0
0
0
standby clear request
standby clear request
standby clear request
standby clear request
Active state of INT8
Active state of INT9
Active state of INTA
Active state of INTB
EMST81
00: －
01: Rising edge
10: Falling edge
11: Both edges
EMST91
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
11
19
27
3
0
0
0
0
R
R
R
R
EMST80
EMST90
10
18
26
2
0
0
0
0
Reads as
undefined.
Reads as
undefined.
Reads as
undefined.
Reads as
undefined.
Undefined
Undefined
Undefined
Undefined
17
25
1
R
9
R
R
R
INT8 clear
input
0: Disable
1: Enable
INT9 clear
input
0: Disable
1: Enable
INTA clear
input
0: Disable
1: Enable
INTB clear
input
0: Disable
1: Enable
INTAEN
INT8EN
INTBEN
TMPM370
INT9EN
Interrupt
R/W
R/W
R/W
R/W
16
24
0
8
0
0
0
0