TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 383

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

(1) When <P3EN> = 1 (<EN0INT> = 0x0002)
(2) When <P3EN> = 0 (<EN0INT> = 0x0002)
19.3.1.2 Sensor Event Count Mode
Encoder Pulse, ENCLK
Encoder Pulse, ENCLK
Encoder Counter
Encoder Counter
・ When <ENCLR> is set to 1, causing the encoder counter to be cleared to 0.
・ <UD> is set to 1 during CW rotation and cleared to 0 during CCW rotation.
・ TIMPLS, which is derived by dividing ENCLK by a programmed factor, can be driven out
・ If <CMPEN> is set to 1, an interrupt is generated when the value of the encoder counter has
・ Clearing <ENRUN> to 0 clears <ZDET> and <UD> to 0.
・ In Sensor Event Count mode, the Hall sensor inputs of the TMPM370 should be connected to the
・ During CW rotation, the encoder counter counts up; when it has reached 0xFFFF, it wraps around
・ During CCW rotation, the encoder counter counts down; when it has reached 0x0000, it wraps
Rotation Direction
Interrupt, INTENC0
Interrupt, INTENC0
Encoder Input, W
Encoder Input, W
Encoder Input, U
Encoder Input, V
Encoder Input, U
Encoder Input, V
Rotation Direction
(÷2) TIMPLS
(÷2) TIMPLS
If the ENCLK and Z edges coincide, the encoder counter is cleared to 0 without incrementing or
decrementing.
externally.
reached the value of <EN0INT>. When <ZEN> = 1, however, an interrupt does not occur while
<ZDET> = 0.
U, V and W channels. The encoder counter counts the pulses of ENCLK, which is either
multiplied_by_4 clock (when <P3EN> = 0) derived from the decoded U and V signals or
multiplied_by_6 clock (when <P3EN> = 1) derived from the decoded U, V and W signals.
to 0 on the next ENCLK.
fsys
fsys
dir
dir
FFFC
FFFC
FFFD
FFFD
FFFE
FFFE
FFFF
FFFF
TMPM370 19-14
0
0
CW
CW
1
1
2
2
3
3
2
2
1
1
0
0
FFFF
FFFF
Encoder Input Circuit
FFFE
FFFE
CCW
CCW
FFFD
FFFD
FFFC
FFFC
TMPM370
FFFB
FFFB
FFFA
FFFA