TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 53

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

recognize interrupt signal in “H” level as interrupt..Interrupt signals directly sent from the peripheral
functions to the CPU are configured to output “H” to indicate an interrupt request.
Interrupt requests from peripheral functions are set as rising-edge or falling-edge triggered. Interrupt
requests from interrupt pins can be set as level-sensitive ("High" or "Low") or edge-triggered (rising or
falling).
is also required. Enable the CGIMCGx<INTxEN> bit and specify the active level in the
CGIMCGx<EMCGx> bits. You must set the active level for interrupt requests from each peripheral
function as shown in Table 7-3.
7.5.1.6
The active level indicates which change in signal of an interrupt source triggers an interrupt. The CPU
Active level is set to the clock generator for interrupts which can be a trigger to release standby.
If an interrupt source is used for clearing a standby mode, setting the relevant clock generator register
An interrupt request detected by the clock generator is notified to the CPU with a signal in “H” level .
No.
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
INTTB30
INTTB31
INTCAP20
INTCAP21
INTCAP30
INTCAP31
INTADASFT
INTADBSFT
INTADATMR
INTADBTMR
INT8
INT9
INTA
INTB
INTENC0
INTENC1
INTRX3
INTTX3
INTTB60
INTTB61
INTTB70
INTTB71
INTCAP60
INTCAP61
INTCAP70
INTCAP71
INTC
INTD
INTE
INTF
Active Level
16bit TMRB3 compare match detection 0/ Over flow
16bit TMRB3 compare match detection 1
16bit TMRB2 input capture 0
16bit TMRB2 input capture 1
16bit TMRB3 input capture 0
16bit TMRB3 input capture 1
ADC unit A conversion started by software is finished
ADC unit B conversion started by software is finished
ADC unit A conversion triggered by timer is finished
ADC unit B conversion triggered by timer is finished
Interrupt Pin (PA7/TB4IN/9pin or 11pin)
Interrupt Pin (PD3/33pin or 35pin)
Interrupt Pin (PL1/21pin or 23pin)
Interrupt Pin (PL0/20pin or 22pin)
Ender input0 interrupt
Ender input1 interrupt
Serial reception (channel.3)
Serial transmit (channel.3)
16bit TMRB6 compare match detection 0 / Over flow
16bit TMRB6 compare match detection 1
16bit TMRB7 compare match detection 0 / Over flow
16bit TMRB7 compare match detection 1
16bit TMRB6 input capture 0
16bit TMRB6 input capture 1
16bit TMRB7 input capture 0
16bit TMRB7 input capture 1
Interrupt Pin (PJ6/AINB9/74pin or 76 pin)
Interrupt Pin (PJ7/AINB10/73pin or 75pin)
Interrupt Pin (PK0/AINB11/72pin or 74pin)
Interrupt Pin (PK1/AINB12/71pin or 73pin)
Table 7-3 List of Hardware Interrupt Sources (2/2)
Interrupt factors
TMPM370 7-15
(Clearing standby)
Active trigger
Edge/Level
Edge/Level
Selectable
Selectable
High/Low
High/Low
mode control
CG interrupt
TMPM370
CGIMCGC
CGIMCGD
Interrupt
register