ADV7393BCPZ Analog Devices Inc, ADV7393BCPZ Datasheet - Page 33

• Manufacturer Part Number: ADV7393BCPZ
• Description: IC DAC VIDEO HDTV 10BIT 40LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7393BCPZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Applications: Set-Top Boxes, Video Players, Displays
• Voltage - Supply, Analog: 2.6 V ~ 3.46 V
• Voltage - Supply, Digital: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADV7393-DBRDZ - BOARD EVAL FOR ADV7393EVAL-ADV7393EBZ - BOARD EVAL FOR ADV7393 ENCODER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 22. Register 0x34 to Register 0x38
SR7 to
SR0
0x34
0x35
0x36
0x37
0x38
1
2
3
4
5
x = Logic 0 or Logic 1.
Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
Applies to the ADV7390 and ADV7392 only.
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
ED/HD Cr level
Register
ED/HD Mode
Register 5
ED/HD Mode
Register 6
ED/HD Y level
ED/HD Cb level
5
5
5
Bit Description
ED/HD timing reset
ED/HD HSYNC control
ED/HD VSYNC control
Reserved
ED Macrovision® enable
Reserved
ED/HD VSYNC input/field
input
ED/HD horizontal/vertical
counter mode
Reserved
Reserved
ED/HD sync on PrPb
ED/HD color DAC swap
ED/HD gamma correction
curve select
ED/HD gamma correction
enable
ED/HD adaptive filter
mode
ED/HD adaptive filter
enable
ED/HD Test Pattern Y level
ED/HD Test Pattern Cr level
ED/HD Test Pattern Cb level
4
2
2
3
7
0
1
0
1
x
x
x
Rev. B | Page 33 of 108
6
0
1
0
1
x
x
x
5
0
1
x
x
0
x
Bit Number
4
0
1
0
1
x
x
x
3
1
0
1
x
x
x
1
2
0
1
0
1
x
x
x
ADV7390/ADV7391/ADV7392/ADV7393
1
0
1
0
x
x
x
0
0
1
0
x
x
x
Register Setting
Internal ED/HD timing counters enabled.
Resets the internal ED/HD timing counters.
HSYNC output control (see
VSYNC output control (see
ED Macrovision disabled.
ED Macrovision enabled.
0 must be written to this bit.
0 = Field input.
1 = VSYNC input.
Update field/line counter.
Field/line counter free running.
Disabled.
Enabled.
DAC 2 = Pb, DAC 3 = Pr
DAC 2 = Pr, DAC 3 = Pb.
Gamma Correction Curve A.
Gamma Correction Curve B.
Disabled.
Enabled.
Mode A.
Mode B.
Disabled.
Enabled.
Y level value.
Cr level value.
Cb level value.
Table 57
Table 56
).
).
Reset
Value
0x48
0x00
0xA0
0x80
0x80