ADV7393BCPZ Analog Devices Inc, ADV7393BCPZ Datasheet - Page 50

• Manufacturer Part Number: ADV7393BCPZ
• Description: IC DAC VIDEO HDTV 10BIT 40LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7393BCPZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Applications: Set-Top Boxes, Video Players, Displays
• Voltage - Supply, Analog: 2.6 V ~ 3.46 V
• Voltage - Supply, Digital: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADV7393-DBRDZ - BOARD EVAL FOR ADV7393EVAL-ADV7393EBZ - BOARD EVAL FOR ADV7393 ENCODER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7390/ADV7391/ADV7392/ADV7393
HD INTERLACE EXTERNAL HSYNC AND VSYNC
CONSIDERATIONS
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01
or higher, the user should set Subaddress 0x02, Bit 1 to high.
To ensure exactly correct timing in HD interlace modes when
using HSYNC and VSYNC synchronization signals. If this bit is
set to low, the first active pixel on each line is masked in HD
interlace modes and the Pr and Pb outputs are swapped when
using the YCrCb 4:2:2 input format. Setting Subaddress 0x02,
Bit 1 to low causes the encoder to behave in the same way as the
first version of silicon (that is, this setting is backward
compatible).
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 00,
the setting of Subaddress 0x02, Bit 1 has no effect. In this
version of the encoder, the first active pixel is masked and the
Pr and Pb outputs are swapped when using YCrCb 4:2:2 input
format. To avoid these limitations, use the newer revision of
silicon or use a different type of synchronization.
These considerations apply only to the HD interlace modes
with external HSYNC and VSYNC synchronization (EAV/SAV
mode is not affected and always has exactly correct timing).
There is no negative effect in setting Subaddress 0x02, Bit 0 to
high, and this bit can remain high for all the other video
standards.
ED/HD TIMING RESET
Subaddress 0x34, Bit 0
An ED/HD timing reset is achieved by setting the ED/HD
timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this
state, the horizontal and vertical counters remain reset. When
this bit is set back to 0, the internal counters resume counting.
This timing reset applies to the ED/HD timing counters only.
SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER
RESET, AND TIMING RESET
Subaddress 0x84, Bits[2:1]
Together with the SFL pin and SD mode Register 4 (Sub-
address 0x84, Bits[2:1]), the ADV739x can be used in timing
reset mode, subcarrier phase reset mode, or SFL mode.
DISPLAY
307
NO TIMING RESET APPLIED
TIMING RESET APPLIED
307
DISPLAY
Figure 64. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits[2:1] = 10)
310
1
START OF FIELD 1
2
3
313
4
START OF FIELD 4 OR 8
Rev. B | Page 50 of 109
5
6
F
7
SC
Timing Reset (TR) Mode
In timing reset (TR) mode (Subaddress 0x84, Bits[2:1] = 10),
a timing reset is achieved in a low-to-high transition on the
SFL pin. In this state, the horizontal and vertical counters
remain reset.
Upon releasing this pin (set to low), the internal counters
resume counting, starting with Field 1, and the subcarrier phase
is reset. The minimum time the pin must be held high is one
clock cycle; otherwise, this reset signal may not be recognized.
This timing reset applies to the SD timing counters only.
Subcarrier Phase Reset (SCR) Mode
In subcarrier reset (SCR) mode (Subaddress 0x84, Bits[2:1] = 01),
a low-to-high transition on the SFL pin resets the subcarrier
phase to 0 on the field following the subcarrier phase reset. This
reset signal must be held high for a minimum of one clock cycle.
Because the field counter is not reset, it is recommended to
apply the reset signal in Field 7 (PAL) or Field 3 (NTSC). The
reset of the phase then occurs on the next field, that is, Field 1,
which is lined up correctly with the internal counters. The field
count register at Subaddress 0xBB can be used to identify the
number of the active field.
Subcarrier Frequency Lock (SFL) Mode
In subcarrier frequency lock (SFL) mode (Subaddress 0x84,
Bits[2:1] = 11), the ADV739x can be used to lock to an external
video source. The SFL mode allows the ADV739x to automatically
alter the subcarrier frequency to compensate for line length
variations. When the part is connected to a device such as an
ADV7403
SFL format, the part automatically changes to the compensated
subcarrier frequency on a line-by-line basis (see Figure 66). This
digital data stream is 67 bits wide, and the subcarrier is contained
in Bit 0 to Bit 21. Each bit is two clock cycles long.
PHASE = FIELD 1
video decoder that outputs a digital data stream in the
21
F
320
SC
PHASE = FIELD 4 OR 8
TIMING RESET PULSE