PI7C8150BMAE Pericom Semiconductor, PI7C8150BMAE Datasheet - Page 40

• Manufacturer Part Number: PI7C8150BMAE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 510 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.8.4.2
3.8.4.3
For posted write transactions:
TARGET DISCONNECT
PI7C8150B returns a target disconnect to an initiator when one of the following conditions
is met:
See Section 3.5.4 for a description of write address boundaries, and Section 3.6.3 for a
description of read address boundaries.
TARGET ABORT
PI7C8150B returns a target abort to an initiator when one of the following conditions is
met:
A locked sequence is being propagated across PI7C8150B, and the read transaction is
not a locked transaction.
PI7C78150B is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
The posted write data buffer does not have enough space for address and at least one
DWORD of write data.
A locked sequence is being propagated across PI7C8150B, and the write transaction is
not a locked transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator
must repeat the transaction with the same address and bus command as well as the data
if it is a write transaction, within the time frame specified by the master timeout value.
Otherwise, the transaction is discarded from the buffers.
PI7C8150B hits an internal address boundary.
PI7C8150B cannot accept any more write data.
PI7C8150B has no more read data to deliver.
PI7C8150B is returning a target abort from the intended target.
When PI7C8150B returns a target abort to the initiator, it sets the signaled target abort
bit in the status register corresponding to the initiator interface.
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B