PI7C8150BMAE Pericom Semiconductor, PI7C8150BMAE Datasheet - Page 57

• Manufacturer Part Number: PI7C8150BMAE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 510 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-2. Setting Secondary Interface Detected Parity Error Bit
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit
Table 6-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C8150B detects a parity
error on the secondary interface.
Table 6-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
Primary Detected
Parity Error Bit
1
0
0
0
X = don’t care
Secondary
Detected
Error Bit
0
1
0
0
0
0
0
1
0
0
0
1
X = don’t care
Primary
Parity Bit
0
0
1
0
0
0
1
0
0
0
1
PI7C8150B must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR_L signal is detected asserted or a parity error is detected on the primary
bus.
Parity
Data
Transaction Type
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Direction
Direction
Downstream
Upstream
Direction
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Bus Where Error
Bus Where Error
Bus Where Error
Was Detected
Was Detected
Was Detected
ADVANCE INFORMATION
April 2009 – Revision 1.08
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x / x
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1 / x
x / x
x / x
x / x
1 / x
x / x
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1 / x
Secondary Parity
Secondary Parity
Secondary Parity
Error Response
Error Response
Error Response
Primary /
Primary/
Primary/
PI7C8150B
Bits
Bits
Bits