PI7C8150BMAE Pericom Semiconductor, PI7C8150BMAE Datasheet - Page 77

• Manufacturer Part Number: PI7C8150BMAE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 510 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.1
14.1.2
14.1.3
VENDOR ID REGISTER – OFFSET 00h
DEVICE ID REGISTER – OFFSET 00h
COMMAND REGISTER – OFFSET 04h
Bit
15:0
Bit
31:16
Bit
0
1
2
3
4
5
6
Function
Vendor ID
Function
Device ID
Function
I/O Space Enable
Memory Space
Enable
Bus Master
Enable
Special Cycle
Enable
Memory Write
And Invalidate
Enable
VGA Palette
Snoop Enable
Parity Error
Response
Type
R/O
Type
R/O
Type
R/W
R/W
R/W
R/O
R/O
R/W
R/W
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Description
Identifies Pericom as vendor of this device. Hardwired as 12D8h.
Description
Identifies this device as the PI7C8150B. Hardwired as 8150h.
Description
Controls response to I/O access on the primary interface
0: ignore I/O transactions on the primary interface
1: enable response to I/O transactions on the primary interface
Reset to 0
Controls response to memory accesses on the primary interface
0: ignore memory transactions on the primary interface
1: enable response to memory transactions on the primary interface
Reset to 0
Controls ability to operate as a bus master on the primary interface
0: do not initiate memory or I/O transactions on the primary
interface and disable response to memory and I/O transactions on
the secondary interface
1: enables 7C8150 to operate as a master on the primary interfaces
for memory and I/O transactions forwarded from the secondary
interface
Reset to 0
No special cycles defined.
Bit is defined as read only and returns 0 when read
Memory write and invalidate not supported.
Bit is implemented as read only and returns 0 when read (unless
forwarding a transaction for another master)
Controls response to VGA compatible palette accesses
0: ignore VGA palette accesses on the primary
1: enable positive decoding response to VGA palette writes on the
primary interface with I/O address bits AD[9:0] equal to 3C6h,
3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded
and may be any value)
Controls response to parity errors
0: 7C8150 may ignore any parity errors that it detects and continue
normal operation
1: 7C8150 must take its normal action when a parity error is
detected
Reset to 0
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B