PI7C8150BMAE Pericom Semiconductor, PI7C8150BMAE Datasheet - Page 91

• Manufacturer Part Number: PI7C8150BMAE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 510 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.41
14.1.42
P_SERR_L STATUS REGISTER – OFFSET 68h
PORT OPTION REGISTER – OFFSET 74h
Bit
16
17
18
19
20
21
22
23
Bit
0
1
2
Function
Address Parity
Error
Posted Write
Data Parity Error
Posted Write
Non-delivery
Target Abort
during Posted
Write
Master Abort
during Posted
Write
Delayed Write
Non-delivery
Delayed Read –
No Data from
Target
Delayed
Transaction
Master Timeout
Function
Reserved
Primary MEMR
Command Alias
Enable
Primary MEMW
Command Alias
Enable
Type
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
Type
R/O
R/W
R/W
Page 91 of 109
Description
1: Signal P_SERR_L was asserted because an address parity error
was detected on P or S bus.
Reset to 0
1: Signal P_SERR_L was asserted because a posted write data parity
error was detected on the target bus.
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver post memory write data to the target after 2
Reset to 0
1: Signal P_SERR_L was asserted because the bridge received a
target abort when delivering post memory write data.
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge received a
master abort when attempting to deliver post memory write data
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver delayed write data after 2
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
read any data from the target after 2
Reset to 0.
1: Signal P_SERR_L was asserted because a master did not repeat a
read or write transaction before master timeout.
Reset to 0.
Description
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150B’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
Controls PI7C8150B’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
24
attempts.
April 2009 – Revision 1.08
24
attempts.
24
attempts.
PI7C8150B