PI7C8150BMAE Pericom Semiconductor, PI7C8150BMAE Datasheet - Page 72

• Manufacturer Part Number: PI7C8150BMAE
• Description: IC PCI-PCI BRIDGE ASYNC 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 510 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12
12.1
12.2
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME#
signals do not pass through PCI-to-PCI bridges.
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
PRIMARY INTERFACE RESET
PI7C8150B has a reset input, P_RESET_L. When P_RESET_L is asserted, the following
events occur:
P_RESET_L asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLKOUT. PI7C8150B is not accessible during P_RESET_L. After P_RESET_L is de-
asserted, PI7C8150B remains inaccessible for 16 PCI clocks before the first configuration
transaction can be accepted.
SECONDARY INTERFACE RESET
PI7C8150B is responsible for driving the secondary bus reset signals, S_RESET_L.
PI7C8150B asserts S_RESET_L when any of the following conditions are met:
Signal P_RESET_L is asserted. Signal S_RESET_L remains asserted as long as
P_RESET_L is asserted and does not de-assert until P_RESET_L is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RESET_L
remains asserted until a configuration write operation clears the secondary reset bit.
S_RESET_L pin is asserted. When S_RESET_L is asserted, PI7C8150B immediately 3-
states all the secondary PCI interface signals associated with the secondary port. The
S_RESET_L in asserting and de-asserting edges can be asynchronous to P_CLK.
When S_RESET_L is asserted, all secondary PCI interface control signals, including the
secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S_PAR
are driven low for the duration of S_RESET_L assertion. All posted write and delayed
transaction data buffers are reset. Therefore, any transactions residing inside the buffers at
the time of secondary reset are discarded.
D3cold
Current Status
PI7C8150B immediately tri-states all primary and secondary PCI interface signals.
PI7C8150B performs a chip reset.
Registers that have default values are reset.
D0
Next State
Page 72 of 109
Power-up reset. PI7C8150B performs the standard power-up reset
functions as described in Section 12.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Action
April 2009 – Revision 1.08
PI7C8150B