MT46H8M32LFB5-6:H Micron Technology Inc, MT46H8M32LFB5-6:H Datasheet - Page 24

IC SDRAM 256MB 166MHZ 90VFBGA

MT46H8M32LFB5-6:H

Manufacturer Part Number
MT46H8M32LFB5-6:H
Description
IC SDRAM 256MB 166MHZ 90VFBGA
Manufacturer
Micron Technology Inc
Series
-r
Type
DDR SDRAMr
Datasheets

Specifications of MT46H8M32LFB5-6:H

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
256M (8Mx32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
6.5/5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
120mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46H8M32LFB5-6:H
Manufacturer:
ST
Quantity:
34 600
Part Number:
MT46H8M32LFB5-6:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Electrical Specifications – AC Operating Conditions
Table 9: Electrical Characteristics and Recommended AC Operating Conditions
Notes 1–9 apply to all parameters in this table; V
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
Parameter
Access window of
DQ from CK/CK#
Clock cycle time
CK high-level width
CK low-level width
CKE minimum pulse width
(high and low)
Auto precharge write recov-
ery + precharge time
DQ and DM input
hold time relative
to DQS
DQ and DM input
hold time relative
to DQS
DQ and DM input
setup time relative
to DQ
DQ and DM input
setup time relative
to DQS
DQ and DM input pulse
width (for each input)
Access window of
DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last
DQ valid, per group, per ac-
cess
WRITE command to first DQS
latching transition
DQS falling edge from CK
rising – hold time
DQS falling edge to CK ris-
ing – setup time
Data valid output window
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
slew
slow
slew
slew
slow
slew
rate
rate
rate
rate
fast
fast
Symbol
t
t
t
DQSCK
t
t
t
DQSH
DQSQ
DVW
DIPW
t
DQSL
DQSS
t
t
t
t
t
t
t
t
t
DAL
DSH
t
CKE
t
DH
DH
DSS
DS
DS
AC
CH
CK
CL
f
s
f
s
Min
0.45
0.45
0.48
0.58
0.48
0.58
0.75
t
2.0
2.0
1.8
2.0
2.0
0.4
0.4
0.2
0.2
12
QH -
5
1
-5
Electrical Specifications – AC Operating Conditions
t
DD
DQSQ
Max
0.55
0.55
1.25
/V
5.0
6.5
5.0
6.5
0.6
0.6
0.4
DDQ
= 1.70–1.95V
Min
0.45
0.45
0.54
0.64
0.54
0.64
0.75
t
2.0
2.0
5.4
1.8
2.0
2.0
0.4
0.4
0.2
0.2
12
QH -
24
1
-54
t
256Mb: x16, x32 Mobile LPDDR SDRAM
DQSQ
Max
0.55
0.55
0.45
1.25
5.0
6.5
5.0
6.5
0.6
0.6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Min
0.45
0.45
0.35
0.35
0.75
t
2.0
2.0
0.6
0.7
0.6
0.7
1.8
2.0
2.0
0.2
0.2
12
QH -
6
1
-6
t
DQSQ
Max
0.55
0.55
1.25
5.0
6.5
5.0
6.5
0.6
0.6
0.5
Min
0.45
0.45
0.75
t
2.0
2.0
7.5
0.8
0.9
0.8
0.9
1.8
2.0
2.0
0.4
0.4
0.2
0.2
12
QH -
1
© 2008 Micron Technology, Inc. All rights reserved.
-75
t
DQSQ
Max
0.55
0.55
1.25
6.0
6.5
6.0
6.5
0.6
0.6
0.6
Unit
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
Notes
13, 14,
13, 14,
13, 17
10
11
12
15
15
16
17

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