MT46H8M32LFB5-6:H Micron Technology Inc, MT46H8M32LFB5-6:H Datasheet - Page 50

• Manufacturer Part Number: MT46H8M32LFB5-6:H
• Description: IC SDRAM 256MB 166MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Series: -r
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:H

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Burst Type
Table 18: Burst Definition Table
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
Length
Burst
16
2
4
8
A3
Starting Column Address
A2
A2
0
0
0
0
1
1
1
1
tions that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4,
8, or 16 locations are available for both sequential and interleaved burst types.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap when a boundary is reached. The block is uniquely
selected by A[i:1] when BL = 2, by A[i:2] when BL = 4, by A[i:3] when BL = 8, and by A[i:4]
when BL = 16, where Ai is the most significant column address bit for a given configura-
tion. The remaining (least significant) address bits are used to specify the starting
location within the block. The programmed burst length applies to both READ and
WRITE bursts.
Accesses within a given burst can be programmed to be either sequential or interleaved
via the standard mode register.
The ordering of accesses within a burst is determined by the burst length, the burst
type, and the starting column address.
A1
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential
50
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
256Mb: x16, x32 Mobile LPDDR SDRAM
0-1
1-0
Order of Accesses Within a Burst
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Standard Mode Register
Type = Interleaved
© 2008 Micron Technology, Inc. All rights reserved.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0