MT46H8M32LFB5-6:H Micron Technology Inc, MT46H8M32LFB5-6:H Datasheet - Page 47

IC SDRAM 256MB 166MHZ 90VFBGA

MT46H8M32LFB5-6:H

Manufacturer Part Number
MT46H8M32LFB5-6:H
Description
IC SDRAM 256MB 166MHZ 90VFBGA
Manufacturer
Micron Technology Inc
Series
-r
Type
DDR SDRAMr
Datasheets

Specifications of MT46H8M32LFB5-6:H

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
256M (8Mx32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
6.5/5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
120mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46H8M32LFB5-6:H
Manufacturer:
ST
Quantity:
34 600
Part Number:
MT46H8M32LFB5-6:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 15: Initialize and Load Mode Registers
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
Command
BA0, BA1
Address
V
DQS
V
DDQ
CK#
CKE
A10
DM
DQ
CK
DD
1
LVCMOS
HIGH LEVEL
Power-up: V
Notes:
NOP 2
T = 200µs
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DD
1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO RE-
2. NOP or DESELECT commands are required for at least 200μs.
3. Other valid commands are possible.
4. NOPs or DESELECTs are required during this time.
and CK stable
t
IS
FRESH command; ACT = ACTIVE command.
NOP
T0
High-Z
High-Z
t
IH
t
CH
t
CK
t
CL
All banks
t
IS
PRE
T1
t
IH
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RP
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AR
Ta0
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256Mb: x16, x32 Mobile LPDDR SDRAM
4
Tb0
AR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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Load standard
mode register
4
t
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Op-code
Op-code
BA0 = L,
IS
IS
IS
BA1 = L
Tc0
LMR
t
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IH
IH
IH
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Load extended
mode register
4
Op-code
Op-code
BA0 = L,
BA1 = H
LMR
Td0
© 2008 Micron Technology, Inc. All rights reserved.
t
MRD
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4
ACT
Te0
Row
Bank
Row
Initialization
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Don’t Care
NOP
Tf0
3

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