MT46H8M32LFB5-6:H Micron Technology Inc, MT46H8M32LFB5-6:H Datasheet - Page 27

• Manufacturer Part Number: MT46H8M32LFB5-6:H
• Description: IC SDRAM 256MB 166MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Series: -r
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:H

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
10. Clock frequency change is only permitted during clock stop, power-down, or self refresh
11. In cases where the device is in self refresh mode for
12.
13. Referenced to each out group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8]. For
14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/
15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and ad-
16. These parameters guarantee device timing but are not tested on each device.
17. The valid data window is derived by achieving other specifications:
18.
19.
20.
21. Fast command/address input slew rate ≥1 V/ns. Slow command/address input slew rate
22. READs and WRITEs with auto precharge must not be issued until
23. The refresh period equals 64ms. This equates to an average refresh rate of 15.6µs for
24. This is not a device limit. The device will operate with a negative value, but system per-
25. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
6. A CK and CK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for
7. All AC timings assume an input slew rate of 1 V/ns.
8. CAS latency definition: with CL = 2, the first data element is valid at (
9. Timing tests may use a V
all parameters.
clock at which the READ command was registered; for CL = 3, the first data element is
valid at (2 ×
timing is still referenced to V
ing reference voltage level is V
mode.
of the clock and ends when CKE transitions HIGH.
t
next highest integer.
x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with
DQ[31:24].
DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to
and
tionality is uncertain.
dresses) are measured between V
V
and
duty cycle and a practical data valid window can be derived. The clock is allowed a maxi-
mum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a
45/55 ratio.
t
CK# inputs, collectively.
t
These parameters are not referenced to a specific voltage level, but specify when the
device output is no longer driving (
t
≥0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated:
tional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns.
added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is
uncertain.
fied prior to the internal PRECHARGE command being issued.
x32; 7.8µs for x16 and x32 reduced page size.
formance could be degraded due to bus turnaround.
The case shown (DQS going from High-Z to logic low) applies when no WRITEs were pre-
viously progress on the bus. If a previous WRITE was in progress, DQS could be HIGH
during this time, depending on
DAL= (
HP (MIN) is the lesser of
HZ and
HZ (MAX) will prevail over
IL(AC)
t
t
DH for each 100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, func-
QH (
for falling input signals.
t
WR/
t
LZ transitions occur in the same access time windows as valid data transitions.
t
HP -
t
t
CK) + (
CK +
Electrical Specifications – AC Operating Conditions
t
QHS). The data valid window derates directly proportional with the clock
t
AC) after the first clock at which the READ command was registered
t
RP/
t
CK): for each term, if not already an integer, round up to the
IL
t
CL (MIN) and
-to-V
27
t
DQSCK (MAX) +
DDQ
IH
DDQ
256Mb: x16, x32 Mobile LPDDR SDRAM
t
/2 or to the crossing point for CK/CK#. The output tim-
DQSS.
swing of up to 1.5V in the test environment, but input
IL(DC)
/2.
t
HZ) or begins driving (
Micron Technology, Inc. reserves the right to change products or specifications without notice.
to V
t
CH (MIN) actually applied to the device CK and
IH(AC)
t
RPST (MAX) condition.
for rising input signals and V
t
CKE,
t
t
CKE starts at the rising edge
LZ).
© 2008 Micron Technology, Inc. All rights reserved.
t
RAS (MIN) can be satis-
t
HP (
t
CK +
t
IS has an addi-
t
t
CK/2),
IH has 0ps
t
AC) after the
IH(DC)
t
DQSQ,
to
t
DS