ISP1362BD NXP Semiconductors, ISP1362BD Datasheet - Page 102

• Manufacturer Part Number: ISP1362BD
• Description: USB Interface IC USB OTG CONTROLLER
• Manufacturer: NXP Semiconductors

Specifications of ISP1362BD

• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1362BD,157

NXP Semiconductors
Table 91.
Table 92.
Table 93.
ISP1362_5
Product data sheet
Bit
31 to 0
Bit
31 to 0 LastPTDBits[31:0]
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
HcINTLPTDSkipMap register: bit description
HcINTLLastPTD register: bit description
HcINTLCurrentActivePTD register: bit allocation
Symbol
SkipBits[31:0] R/W
14.8.6 HcINTLLastPTD register (R/W: 19h/99h)
14.8.7 HcINTLCurrentActivePTD register (R: 1Ah)
15
7
-
-
-
-
PTD if the HCD has reset its corresponding skipped bit to logic 0. Clearing the
corresponding bit in the HcINTLPTDSkipMap register when there is no valid data in the
block will cause unpredictable behavior of the Host Controller.
Code (Hex): 18 — read
Code (Hex): 98 — write
This is a 32-bit register, and
represents the first PTD stored in the INTL buffer, bit 1 represents the second PTD stored
in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an indication to
the Host Controller that its corresponding PTD is the last PTD stored in the INTL buffer.
When the processing of the last PTD is complete, the Host Controller proceeds to process
ATL transactions.
Code (Hex): 19 — read
Code (Hex): 99 — write
This register indicates which PTD stored in the INTL buffer is currently active and is
updated by the Host Controller. The HCD can use it as a buffer pointer to decide which
PTD locations are currently free to fill in new PTDs to the buffer. This indication is to
prevent the HCD from accidentally writing into the currently active PTD buffer location.
Table 93
Code (Hex): 1A — read only
Access
reserved
Access
R/W
14
6
-
-
-
-
shows the bit allocation of the register.
Value
0000h
Value
0000h
13
5
-
-
-
-
Description
0 — The Host Controller processes the PTD.
1 — The Host Controller skips processing the PTD.
Rev. 05 — 8 May 2007
Description
0 — The PTD is not the last PTD stored in the buffer.
1 — The PTD is the last PTD stored in the buffer.
Table 92
12
R
4
0
-
-
reserved
shows its bit description. Bit 0 of the register
11
R
3
0
-
-
ActivePTD[4:0]
Single-chip USB OTG Controller
10
R
2
0
-
-
R
9
1
0
-
-
© NXP B.V. 2007. All rights reserved.
ISP1362
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R
8
0
0
-
-