ISP1362BD NXP Semiconductors, ISP1362BD Datasheet - Page 8

• Manufacturer Part Number: ISP1362BD
• Description: USB Interface IC USB OTG CONTROLLER
• Manufacturer: NXP Semiconductors

Specifications of ISP1362BD

• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1362BD,157

NXP Semiconductors
Table 2.
ISP1362_5
Product data sheet
Symbol
DGND
D2
D3
V
D4
D5
D6
D7
DGND
D8
D9
D10
D11
CC
[1]
Pin description
Pin
LQFP64
1
2
3
4
5
6
7
8
9
10
11
12
13
6.2 Pin description
TFBGA64
B1
C2
C1
D2
D1
E2
E1
F2
F1
G2
G1
H2
H1
Type
-
I/O
I/O
-
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
Description
digital ground
bit 2 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
bit 3 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
supply voltage (3.3 V); it is recommended that you connect a decoupling
capacitor of 0.01 F
bit 4 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
bit 5 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
bit 6 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
bit 7 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
digital ground
bit 8 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
bit 9 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
bit 10 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
bit 11 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, 3-state output
Rev. 05 — 8 May 2007
Single-chip USB OTG Controller
© NXP B.V. 2007. All rights reserved.
ISP1362
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