ISP1362BD NXP Semiconductors, ISP1362BD Datasheet - Page 27

• Manufacturer Part Number: ISP1362BD
• Description: USB Interface IC USB OTG CONTROLLER
• Manufacturer: NXP Semiconductors

Specifications of ISP1362BD

• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1362BD,157

NXP Semiconductors
ISP1362_5
Product data sheet
8.6.2 Combining the two DMA channels
8.7.1 Interrupt in the Host Controller and the OTG Controller
8.7 Interrupts
Remark: Configure the HcDMAConfiguration register only after you have configured all
the other registers. The ISP1362 will assert DREQ1 once the DMA enable bit in this
register is set.
The ISP1362 allows systems with limited DMA channels to use a single DMA channel
(DMA1) for both the Host Controller and the Peripheral Controller. This option can be
enabled by writing logic 1 to the OneDMA bit of the HcHardwareConfiguration register. If
this option is enabled, the polarity of the Peripheral Controller DMA and the Host
Controller DMA must be set to DACK active LOW and DREQ active HIGH.
Various events in the Host Controller, the Peripheral Controller and the OTG Controller
can be programmed to generate a hardware interrupt. By default, the interrupt generated
by the Host Controller and the OTG Controller is routed out at the INT1 pin and the
interrupt generated by the Peripheral Controller is routed out at the INT2 pin.
There are two levels of interrupts represented by level 1 and level 2 (see
•
•
HcTransferCounter
– If DMACounterEnable of the HcDMAConfiguration register is set (that is, the DMA
HcDMAConfiguration
– Read or write DMA (bit 0)
– Targeted buffer: ISTL0, ISTL1, ATL and INTL (bits 1 to 3)
– DMA enable or disable (bit 4)
– Burst length (bits 5 to 6)
– DMA counter enable (bit 7)
counter is enabled), HcTransferCounter must be set to the number of bytes to be
transferred.
Rev. 05 — 8 May 2007
Single-chip USB OTG Controller
© NXP B.V. 2007. All rights reserved.
ISP1362
Figure
14).
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