ISP1362BD NXP Semiconductors, ISP1362BD Datasheet - Page 11

• Manufacturer Part Number: ISP1362BD
• Description: USB Interface IC USB OTG CONTROLLER
• Manufacturer: NXP Semiconductors

Specifications of ISP1362BD

• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1362BD,157

NXP Semiconductors
Table 2.
ISP1362_5
Product data sheet
Symbol
H_PSW1
H_PSW2
DGND
CLKOUT
GL
V
H_OC2
H_OC1
X1
X2
OTGMODE
H_DM2
H_DP2
ID
CC
[1]
Pin description
Pin
LQFP64
35
36
37
38
39
40
41
42
43
44
45
46
47
48
TFBGA64
H10
G9
G10
F9
F10
E9
E10
D9
D10
C9
C10
B9
B10
A10
…continued
Type
O
O
-
O
O
-
I
I
AI
AO
I
AI/O
AI/O
I
Description
connects to the external PMOS switch; required when the external
charge pump or external V
downstream port
LOW — switches on the PMOS providing V
HIGH — switches off the PMOS
when not in use, leave this pin open
open-drain output
connects to the external PMOS switch
LOW — switches on the PMOS providing V
HIGH — switches off the PMOS
when not in use, leave this pin open
open-drain output
digital ground
programmable clock output; the default clock frequency is 12 MHz and
can be varied from 3 MHz to 48 MHz
push-pull output
GoodLink LED indicator output; the LED is off by default, blinks on at
USB traffic
open-drain output; 4 mA
supply voltage (3.3 V); it is recommended that you connect a decoupling
capacitor of 0.01 F
overcurrent sense input for downstream port 2; both the digital and
analog overcurrent inputs can be used for port 2, depending on the
hardware mode register setting; when not in use, it is recommended that
you connect this pin to the V
overcurrent sensing input for downstream port 1; both the digital and
analog overcurrent inputs can be used for port 1, depending on the
hardware mode register setting; when not in use, it is recommended that
you connect this pin to the V
crystal input; directly connected to a 12 MHz crystal; when this pin is
connected to an external clock oscillator, leave pin X2 open
crystal output; directly connected to a 12 MHz crystal; when pin X1 is
connected to an external clock oscillator, leave this pin open
to select whether port 1 is operating in OTG or non-OTG mode; see
Table 8
input with hysteresis
downstream D signal; host only, port 2; when not in use, leave this pin
open and set bit ConnectPullDown_DS2 of the
HcHardwareConfiguration register
downstream D+ signal; host only, port 2; when not in use, leave this pin
open and set bit ConnectPullDown_DS2 of the
HcHardwareConfiguration register
input pin for sensing OTG ID; the status of this input pin is reflected in the
OTGStatus register (bit 0); see
input with hysteresis
Rev. 05 — 8 May 2007
BUS
DD(5V)
DD(5V)
is used for providing V
Table 8
pin
pin
Single-chip USB OTG Controller
BUS
BUS
to the downstream port
to the downstream port
© NXP B.V. 2007. All rights reserved.
BUS
ISP1362
to the
10 of 152