ISP1362BD NXP Semiconductors, ISP1362BD Datasheet - Page 96

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ISP1362BD

Manufacturer Part Number
ISP1362BD
Description
USB Interface IC USB OTG CONTROLLER
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1362BD

Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
 Details
Other names
ISP1362BD,157

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NXP Semiconductors
Table 74.
Table 75.
Table 76.
ISP1362_5
Product data sheet
Bit
15 to 0
Bit
15 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcScratch register: bit description
HcSoftwareReset register: bit description
HcBufferStatus register: bit allocation
Symbol
ResetValue[15:0] W
Symbol
Scratch[15:0]
14.5.3 HcSoftwareReset register (W: A9h)
14.6.1 HcBufferStatus register (R/W: 2Ch/ACh)
reserved
14.6 HC buffer RAM control registers
15
7
-
-
-
-
This register provides a means for the software reset of the Host Controller. To reset the
Host Controller, the HCD must write a reset value of F6h to this register. On receiving this
reset value, the Host Controller resets all the Host Controller and OTG registers, except its
buffer memory.
Table 75
Code (Hex): A9 — write only
The bit allocation of the HcBufferStatus register is given in
Code (Hex): 2C — read
Code (Hex): AC — write
Table 77.
Bit
15 to 11 -
10
9
ISTL1_
Status
Active
Access
14
R
6
0
-
-
Access
R/W
contains the bit description of the register.
Symbol
PairedPTDPingPong 0 — Ping of the paired PTD in ATL is active.
ISTL1BufferDone
HcBufferStatus register: bit description
Value
0000h
reserved
ISTL0_
Status
Active
13
R
5
0
-
-
Value
0000h
Rev. 05 — 8 May 2007
Description
Writing a reset value of F6h causes the Host Controller to reset all the
Host Controller and OTG registers, except its buffer memory.
Reset_HW
PingPong
Description
reserved
1 — Pong of the paired PTD in ATL is active.
0 — The ISTL1 buffer has not yet been read by the Host
Controller.
1 — The ISTL1 buffer has been read by the Host Controller.
R/W
Reg
12
4
0
-
-
Description
scratch register value.
ATL_Active
R/W
11
3
0
-
-
PairedPTD
PingPong
Single-chip USB OTG Controller
INTL_
Active
R/W
10
R
0
2
0
Table
76.
BufferDone
BufferFull
ISTL1
ISTL1
R/W
R
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
BufferDone
BufferFull
ISTL0
ISTL0
R/W
95 of 152
R
8
0
0
0

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