PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 45

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

2.0 Device Architecture and Configuration
2.10.10 SuperI/O Configuration 9 Register (SIOCF9)
Location:
Type:
Bit
Name
Reset
7-5
1-0
Bit
4
3
2
Reserved
Module Enable Status. This bit defines the status of all the PC8739x modules with exception of the X-Bus. This
bit is read only.
0: All modules disabled
1: At least one module enabled
Valid Multiplier Clock Status. This bit is read only.
0: On-chip clock frozen
1: On-chip clock stable and toggling
Clock Enable. This bit enables the 48 and 24 MHz clock to the SuperI/O modules. When the SuperI/O chip
clock source is set to 48 MHz, this bit enables the path from the input CLKIN pin. When the clock source is set
to 32.768 KHz or 14.31818 MHz, this bit enables the clock multiplier.This is a read/write bit that is reset by
hardware reset only.
0: Clock disabled (default)
1: Clock enabled
SuperI/O Chip Clock Source. These bits define the clock source for the SuperI/O chip that is fed via the CLKIN
pin. On power-up (only), these bits are read or write and assume their default value. Once they are written, they
become read only bits.
Bits
1 0
0 0
0 1
1 0
1 1
Index 29h
Varies per bit
Function
Clock source is 48 MHz
Clock source is the on-chip clock multiplier fed by 32.768 KHz
Clock source is the on-chip clock multiplier fed by 14.31818 MHz (default)
Reserved
7
0
Reserved
6
0
5
Module
Enable
Status
Description
45
4
0
(Continued)
Valid Multi-
plier Clock
Status
3
0
Enable
Clock
2
0
SuperI/O Chip Clock
1
1
Source
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