PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 91
PC87393VJG
Manufacturer Part Number
PC87393VJG
Description
IC, SUPER I/O DEVICE, TQFP-100
Manufacturer
National Semiconductor
Specifications of PC87393VJG
Data Rate
2Mbps
Supply Voltage Range
3V to 3.6V
Logic Case Style
TQFP
No. Of Pins
100
Operating Temperature Range
0°C to +70°C
Termination Type
SMD
Transceiver Type
Interface
Rohs Compliant
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PC87393VJG
Manufacturer:
NS/国半
Quantity:
20 000
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5.0 Game Port (GMP)
5.3.5
This register defines the conditions on which the Game Port asserts its interrupt request signal.
This register is functional only in Enhanced mode.
Location:
Type:
Bit
Name
Reset
Bit
7
6
5
4
3
2
1
0
Game Port Interrupt Enable Register (GMPIEN)
Device B Button 1 IRQ Enable. When set to 1, the Game Port issues an interrupt request in response to an
event triggered by Button 1 of Device B. When set to 0, Button 1 of Device B cannot cause interrupt requests to
be issued.
0: Disabled (default)
1: Enabled
Device B Button 0 IRQ Enable. Same as bit 7 of this register, but for Device B Button 0.
0: Disabled (default)
1: Enabled
Device A Button 1 IRQ Enable. Same as bit 7 of this register, but for Device A Button 1.
0: Disabled (default)
1: Enabled
Device A Button 0 IRQ Enable. Same as bit 7 of this register, but for Device A Button 0.
0: Disabled (default)
1: Enabled
Reserved
Position IRQ Event Definition Defines the event on which the position IRQ is asserted for both game devices.
0: Both X-Position Counter and Y-Position Counter are ready
1: Either X-Position Counter or Y-Position Counter is ready
Device B Position IRQ Enable. When set to 1, the Game Port issues an interrupt request when the position
reading of Device B is completed and the position counters can be read. When set to 0, no interrupt request is
issued in response to any change in the status of Device B position counters.
0: Disabled (default)
1: Enabled
Device A Position IRQ Enable. Same as bit 2 of this register, but for Device A.
0: Disabled (default)
1: Enabled
Offset 03h
R/W
IRQ Enable
Device B
Button 1
7
0
IRQ Enable
Device B
Button 0
(Continued)
6
0
IRQ Enable
Device A
Button 1
5
0
IRQ Enable
Device A
Button 0
Description
91
4
0
Reserved
3
0
IRQ Event
Definition
Position
2
0
IRQ Enable
Device B
Position
1
0
IRQ Enable
Device A
www.national.com
Position
0
0
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