AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 34

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5. Memories
5.1
5.2
32072G–11/2011
Embedded Memories
Physical Memory Map
•
•
The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot.
Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Techni-
cal Architecture Manual.
The 32-bit physical address space is mapped as follows:
Table 5-1.
Device
Embedded CPU SRAM
Embedded Flash
EBI SRAM CS0
EBI SRAM CS2
EBI SRAM CS3
EBI SRAM CS4
EBI SRAM CS5
EBI SRAM CS1
/SDRAM CS0
USB Data
Internal High-Speed Flash
Internal High-Speed SRAM
– 256KBytes (AT32UC3A3256/S)
– 128Kbytes (AT32UC3A3128/S)
– 64Kbytes (AT32UC3A364/S)
– 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the
– 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix
High Speed Bud (HSB) matrix
• 0 wait state access at up to 36MHz in worst case conditions
• 1 wait state access at up to 66MHz in worst case conditions
• Pipelined Flash architecture, allowing burst reads from sequential Flash locations, hiding
• Pipelined Flash architecture typically reduces the cycle penalty of 1 wait state operation
• 100 000 write cycles, 15-year data retention capability
• Sector lock capabilities, Bootloader protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User page for data to be preserved during Chip Erase
penalty of 1 wait state access
to only 15% compared to 0 wait state operation
AT32UC3A3A4 Physical Memory Map
Start
Address
0x00000000
0x80000000
0xC0000000
0xC8000000
0xD8000000
0xD0000000
0xE0000000
0xCC000000
0xDC000000
Size
AT32UC3A3256S
AT32UC3A3256
AT32UC3A4256S
AT32UC3A4256
64KByte
256KByte
16MByte
16MByte
16MByte
16MByte
16MByte
128MByte
64KByte
Size
AT32UC3A3128S
AT32UC3A3128
AT32UC3A4128S
AT32UC3A4128
64KByte
128KByte
16MByte
16MByte
16MByte
16MByte
16MByte
128MByte
64KByte
Size
AT32UC3A364S
AT32UC3A364
AT32UC3A464S
AT32UC3A464
64KByte
64KByte
16MByte
16MByte
16MByte
16MByte
16MByte
128MByte
64KByte
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