AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 57

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.11
7.11.1
Table 7-29.
Note:
Table 7-30.
Note:
32072G–11/2011
Symbol
1/(t
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
CPSMC
1
2
3
4
5
7
8
9
10
11
12
13
14
16
17
18
EBI Timings
1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold
)
SMC Signals
length”.
SMC Clock Signal
SMC Read Signals with Hold Settings
Parameter
SMC Controller Clock Frequency
Parameter
Data Setup before NRD High
Data Hold after NRD High
NRD High to NBS0/A0 Change
NRD High to NBS1 Change
NRD High to NBS2/A1 Change
NRD High to A2 - A23 Change
NRD High to NCS Inactive
NRD Pulse Width
Data Setup before NCS High
Data Hold after NCS High
NCS High to NBS0/A0 Change
NCS High to NBS0/A0 Change
NCS High to NBS2/A1 Change
NCS High to A2 - A23 Change
NCS High to NRD Inactive
NCS Pulse Width
These timings are given for worst case process, T = 85⋅C, VDDIO = 3V and 40 pF load
capacitance.
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
NRD Controlled (READ_MODE = 1)
NRD Controlled (READ_MODE = 0)
(nrd hold length - ncs rd hold length) * t
ncs rd hold length - nrd hold length)* t
ncs rd hold length * t
ncs rd hold length * t
ncs rd hold length * t
ncs rd pulse length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
ncs rd hold length * t
nrd pulse length * t
nrd hold length * t
Min.
11.5
12
0
0
CPSMC
1/(t
CPSMC
CPSMC
CPSMC
CPSMC
Max.
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
cpcpu
(1)
- 1.3
- 1.4
-
-
-
- 2.3
)
- 3.6
1.3
1.3
1.3
-
-
CPSMC
-
CPSMC
2.3
2.3
4
- 1.3
- 2.3
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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