AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 60

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 7-8.
7.11.2
Table 7-34.
Note:
Table 7-35.
32072G–11/2011
A0/A1/NBS[3:0]
Symbol
1/(t
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
CPSDCK
D0 - D15
A2-A25
NWE
NRD
NCS
1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB.
)
1
2
3
4
5
6
7
8
9
10
11
12
SDRAM Signals
SMC Signals for NRD and NRW Controlled Accesses.
SDRAM Clock Signal.
SDRAM Clock Signal
Parameter
SDRAM Controller Clock Frequency
Parameter
SDCKE High before SDCK Rising Edge
SDCKE Low after SDCK Rising Edge
SDCKE Low before SDCK Rising Edge
SDCKE High after SDCK Rising Edge
SDCS Low before SDCK Rising Edge
SDCS High after SDCK Rising Edge
RAS Low before SDCK Rising Edge
RAS High after SDCK Rising Edge
SDA10 Change before SDCK Rising Edge
SDA10 Change after SDCK Rising Edge
Address Change before SDCK Rising Edge
Address Change after SDCK Rising Edge
These timings are given for 10 pF load on SDCK and 40 pF on other signals.
SMC9
SMC19
SMC7
SMC20
SMC3
SMC4
SMC5
SMC6
SMC8
SMC45
SMC43
SMC42
SMC37
SMC38
SMC39
SMC40
SMC41
SMC44
Conditions
Conditions
SMC9
SMC1
SMC2
SMC8
SMC7
SMC3
SMC4
SMC5
SMC6
Min.
Min.
7.4
3.2
2.9
7.5
1.6
7.2
2.3
7.6
1.9
6.2
2.2
7
SMC33
1/(t
SMC23
Max.
Max.
cpcpu
(1)
SMC24
SMC32
)
SMC31
SMC25
SMC26
SMC29
SMC30
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60