AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 225

• Manufacturer Part Number: AT32UC3A464S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464S

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 16-5. Read Burst, 16-bit SDRAM Access
16.7.4
32072G–11/2011
SDRAMC_A[12:0]
Border Management
D[15:0]
SDWE
(Input)
SDCS
SDCK
RAS
CAS
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAMC generates a precharge command, activates the new row and initiates a read
or write command. To comply with SDRAM timing parameters, an additional clock cycle is
inserted between the precharge and active (t
(t
RCD
) commands. This is described in
Row n
t
RCD
= 3
Col a
CAS = 2
Col b
Figure 16-6 on page
Dna
Col c
RP
Dnb
) commands and between the active and read
Col d
Dnc
Col e
226.
Dnd
Col f
Dne
Dnf
225