AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 318

• Manufacturer Part Number: AT32UC3A464S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464S

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
Transfer hierarchy:
fers, block transfers, transactions (single or burst), and System Bus transfers (single or burst) for
non-memory peripherals.
Figure 19-2. DMACA Transfer Hierarchy for Non-Memory Peripheral
Figure 19-3. DMACA Transfer Hierarchy for Memory
Block: A block of DMACA data. The amount of data (block length) is determined by the flow
controller. For transfers between the DMACA and memory, a block is broken directly into a
sequence of System Bus bursts and single transfers. For transfers between the DMACA and a
non-memory peripheral, a block is broken into a sequence of DMACA transactions (single and
bursts). These are in turn broken into a sequence of System Bus transfers.
Transaction: A basic unit of a DMACA transfer as determined by either the hardware or soft-
ware handshaking interface. A transaction is only relevant for transfers between the DMACA
and a source or destination peripheral if the source or destination peripheral is a non-memory
device. There are two types of transactions: single and burst.
System Bus
Transaction
Transfer
Burst
Block
Burst
System Bus
Transfer
Burst
Block
System Bus
Transaction
Transfer
Burst
Figure 19-2 on page 318
Burst
Block
System Bus
DMAC Transfer
Figure 19-3 on page 318
Transfer
Burst
Block
DMAC Transfer
System Bus
Transfer
Transaction
Burst
Burst
System Bus
Transfer
Block
Burst
System Bus
illustrates the hierarchy between DMACA trans-
Transfer
Single
Block
shows the transfer hierarchy for memory.
System Bus
Transfer
Single
System Bus
Transaction
Transfer
Single
Single
Block Transfer
Level
System Bus
Transfer Level
DMA Transfer
Level
Block Transfer
Level
DMA Transaction
Level
System Bus
Transfer Level
DMA Transfer
Level
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