AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 885

• Manufacturer Part Number: AT32UC3A464S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464S

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.4.2
32.4.2.1
32.4.2.2
32072G–11/2011
Start Modes
Manual mode
Automatic mode
These sizes are selected by writing the Cipher Feedback Data Size field in the MR register
(MR.CFDS).
The Start Mode field in the MR register (MR.SMOD) allows selection of the encryption (or
decryption) start mode.
The sequence is as follows:
Note:
Table 32-1.
Note:
Note:
The automatic mode is similar to the manual one, except that in this mode, as soon as the cor-
rect number of IDATAnR Registers is written, processing is automatically started without any
action in the CR register.
• Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.
• Write the initialization vector (or counter) in the IVnR registers.
• Write the Data Ready bit in the Interrupt Enable Register (IER.DATRDY), depending on
• Write the data to be encrypted/decrypted in the authorized Input Data Registers (IDATAnR).
• Write the START bit in the Control Register (CR.START) to begin the encryption or the
• When the processing completes, the DATRDY bit in the Interrupt Status Register
• If an interrupt has been enabled by writing the IER.DATRDY bit, the interrupt line of the AES
• When the software reads one of the Output Data Registers (ODATAxR), the ISR.DATRDY bit
whether an interrupt is required or not at the end of processing.
decryption process.
(ISR.DATRDY) is set.
is activated.
is cleared.
Operation Mode
128-bit CFB
64-bit CFB
32-bit CFB
16-bit CFB
8-bit CFB
The Initialization Vector Registers concern all modes except ECB.
In 64-bit CFB mode, writing to IDATA3R and IDATA4R registers is not allowed and may lead to
errors in processing.
In 32-bit, 16-bit and 8-bit CFB modes, writing to IDATA2R, IDATA3R and IDATA4R registers is not
allowed and may lead to errors in processing.
ECB
CBC
OFB
CTR
Authorized Input Data Registers
IDATA1R and IDATA2R
IDATAnR to Write
IDATA1R
IDATA1R
IDATA1R
All
All
All
All
All
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