AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 352

• Manufacturer Part Number: AT32UC3A464S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464S

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.12.4
Name:
Access Type:
Offset:
Reset Value:
This register contains fields that control the DMA transfer. The CTLxL register is part of the block descriptor (linked list item)
when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is
enabled.
• LLP_SRC_EN
Block chaining is only enabled on the source side if the LLP_SRC_EN field is high and LLPx.LOC is non-zero.
• LLP_DST_EN
Block chaining is only enabled on the destination side if the LLP_DST_EN field is high and LLPx.LOC is non-zero.
• SMS: Source Master Select
Identifies the Master Interface layer where the source device (peripheral or memory) is accessed from
Table 19-4.
32072G–11/2011
SMS
0
1
Other
DINC[0]
DMS[0]
31
23
15
7
SRC_MSIZE[1:0]
Control Register for Channel x Low
Source Master Select
HSB Master
HSB master 1
HSB master 2
Reserved
30
22
14
6
CTLxL
Read/Write
0x018 + [x * 0x58]
0x00304801
SRC_TR_WIDTH
TT_FC
29
21
13
5
DEST_MSIZE
LLP_SRC_E
28
20
12
N
4
LLP_DST_E
27
19
11
N
3
DST_TR_WIDTH
DST_GATHE
R_EN
26
18
10
2
SINC
SMS
SRC_GATH
ER_EN
25
17
9
1
SRC_MSIZE
DINC[1]
INT_EN
DMS[1]
24
16
[2]
8
0
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