ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 185

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.7.6
15.7.7
15.7.8
15.7.9
8077H–AVR–12/09
DTBOTHBUF - Dead-time Concurrent Write to Both Sides Buffer
DTLS - Dead-Time Low Side Register
DTHS - Dead-Time High Side Register
DTLSBUF - Dead-Time Low Side Buffer Register
• Bit 7:0 - DTBOTH: Dead-Time Both Sides
Writing to this register will update both DTHS and DTLS registers at the same time (i.e. at the
same I/O write access).
• Bit 7:0 - DTBOTHBUF: Dead-Time Both Sides Buffer
Writing to this memory location will update both DTHSBUF and DTLSBUF registers at the same
time (i.e. at the same I/O write access).
• Bit 7:0 - DTLS: Dead-Time Low Side
This register holds the number of peripheral clock cycles for the Dead-Time Low Side.
• Bit 7:0 - DTHS: Dead-Time High Side
This register holds the number of peripheral clock cycles for the Dead-Time High Side.
• Bit 7:0 - DTLSBUF: Dead-Time Low Side Buffer
This register is the buffer for the DTLS Register. If double buffering is used, valid contents in this
register is copied to the DTLS Register on an UPDATE condition.
Bit
+0x07
Read/Write
Initial Value
Bit
+0x0A
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
DTBOTHBUF[7:0]
R/W
R/W
4
0
R/W
4
0
4
0
4
0
DTLSBUF[7:0]
DTHS[7:0]
DTLS[7:0]
R/W
3
0
R/W
R/W
R/W
3
0
3
0
3
0
R/W
2
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
1
0
R/W
R/W
R/W
1
0
1
0
1
0
XMEGA A
R/W
0
0
R/W
R/W
R/W
0
0
0
0
0
0
DTBOTHBUF
DTLSBUF
DTHS
DTLS
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