ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 28

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.15.10
4.15.11
8077H–AVR–12/09
INTCTRL - Non-Volatile Memory Interrupt Control Register
STATUS - Non-Volatile Memory Status Register
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 - SPMLVL[1:0]: SPM Ready Interrupt Level
These bits enable the Interrupt and select the interrupt level as described in
grammable Multi-level Interrupt Controller” on page
will be triggered when the BUSY flag in the STATUS is set to logical 0. Since the interrupt is a
level interrupt note the following.
The interrupt should not be enabled before triggering a NVM command, as the BUSY flag wont
be set before the NVM command is triggered. Since the interrupt trigger is a level interrupt, the
interrupt should be disabled in the interrupt handler.
• Bit 1:0 - EELVL[1:0]: EEPROM Ready Interrupt Level
These bits enable the EEPROM Ready Interrupt and select the interrupt level as described in
”Interrupts and Programmable Multi-level Interrupt Controller” on page
level interrupt, which will be triggered when the BUSY flag in the STATUS is set to logical 0.
Since the interrupt is a level interrupt note the following.
The interrupt should not be enabled before triggering a NVM command, as the BUSY flag wont
be set before the NVM command is triggered. Since the interrupt trigger is a level interrupt, the
interrupt should be disabled in the interrupt handler.
• Bit 7 - NVMBUSY: Non-Volatile Memory Busy
The NVMBSY flag indicates whether the NVM memory (FLASH, EEPROM, Lock-bits) is busy
being programmed. Once a program operation is started, this flag will be set and it remains set
until the program operation is completed. he NVMBSY flag will automatically be cleared when
the operation is finished.
• Bit 6 - FBUSY: Flash Section Busy
The FBUSY flag indicate whether a Flash operation (Page Erase or Page Write) is initiated.
Once a operation is started the FBUSY flag is set, and the Application Section cannot be
accessed. The FBUSY bit will automatically be cleared when the operation is finished.
Bit
+0x0D
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
BUSY
R
R
7
0
7
0
-
FBUSY
R
R
6
0
6
0
-
R
5
0
-
R
5
0
-
R
4
0
-
R
4
0
-
R
3
0
-
123. The interrupt is a level interrupt, which
R/W
3
0
SPMLVL[1:0]
R
2
0
-
R/W
2
0
EELOAD
R
1
0
R/W
1
0
EELVL[1:0]
123. The interrupt is a
”Interrupts and Pro-
XMEGA A
FLOAD
R
R/W
0
0
0
0
INTCTRL
STATUS
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