ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 346

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.3.1
29.3.2
29.3.3
8077H–AVR–12/09
Enabling
Disabling
Frame Format and Characters
The remainder of this section is only intended for third parties developing programming support
for XMEGA.
The PDI Physical must be enabled before it can be used. This is done by first forcing the
PDI_DATA line high for a period longer than the equivalent external reset minimum pulse width
(refer to device data sheet for external reset pulse width data). This will disable the RESET func-
tionality of the Reset pin, if not already disabled by the fuse settings.
In the next step of the enabling procedure the PDI_DATA line must be kept high for 16 PDI_CLK
cycles (16 positive edges detected). The first PDI_CLK cycle must start no later than 100uS
after the RESET functionality of the Reset pin was disabled. If this does not occur in time the
RESET functionality of the Reset pin is automatically enabled again and the enabling procedure
must start over again.
After this the PDI is enabled and ready to receive instructions. The enable sequence is shown in
Figure 29-3 on page
The RESET pin is sampled when the PDI interface is enabled. The RESET register is then set
according to the state of the RESET pin, preventing the device from running code after the reset-
functionality of this pin is disabled.
The PDI_DATA pin has an internal pull-down resistor.
Figure 29-3. Sequence for enabling the PDI.
If the clock frequency on the PDI_CLK is lower than approximately 10 kHz, this is regarding as
inactivity on the clock line. This will then automatically disable the PDI. If not disabled by fuse,
the RESET function on the Reset (PDI_CLK) pin is automatically enabled again. If the time-out
occurs during the PDI enabling sequence, the whole sequence must be started from the
beginning.
This also means that the minimum programming frequency is approximately 10 kHz.
The PDI physical layer uses a fixed frame format. A serial frame is defined to be one character
of eight data bits with start and stop bits and a parity bit.
Figure 29-4. PDI serial frame format.
PDI_DATA
PDI_CLK
(IDLE)
St
Disable RESET function on Reset (PDI_CLK) pin
346.
0
1
2
3
4
FRAME
5
6
7
P
Sp1
Activate PDI
Sp2
XMEGA A
(St/IDLE)
346