ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 379

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.12 External Programming
8077H–AVR–12/09
External Programming is the method for programming non volatile code and data into the device
from an external programmer or debugger. This can be done both in-system (In-System Pro-
gramming) or in mass production programming. The only restrictions on clock speed and voltage
is the maximum and minimum operating conditions for the device. Refer to the device data sheet
for details on this.
For external programming the device is accessed through the PDI and PDI Controller, using
either the JTAG or PDI physical connection. For details on PDI and JTAG and how to enable
and use the physical interface, refer to
remainder of this section assumes that the correct physical connection to the PDI is enabled.
Through the PDI, the external programmer access all NVM memories and NVM Controller using
the PDI Bus. Doing this all data and program memory spaces are mapped into the linear PDI
memory space.
for each memory space in the device.
Figure 30-4 on page 380
”Program and Debug Interface” on page
shows the PDI memory space and the base address
XMEGA A
344. The
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