ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 265

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.5.2
23.5.3
8077H–AVR–12/09
STATUS - AES Status Register
STATE - AES State Register
• Bit 1:0 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 7 - ERROR: AES Error
The ERROR flag indicates an illegal handling of the AES Crypto Module. The flag is set in the
following cases:
This flag can be cleared by software by writing one to its bit location.
• Bit 6:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - SRIF: AES State Ready Interrupt flag
This flag is the interrupt/DMA request flag and is set when the encryption/decryption procedure
is completed and the State memory contains valid data. As long as the flag is zero this indicates
that there is no valid encrypted/decrypted data in the state memory.
The flag is cleared by hardware when a read access is made to the State memory (the first byte
is read). Alternatively the bit can be cleared by writing a one to its bit location
The State Register is used to access the State memory. Before encryption/decryption can take
place the State memory must be written sequentially byte by byte through the State Register.
After encryption/decryption is done the ciphertext/plaintext can be read sequentially byte by byte
through the State Register.
Loading the initial data to the State Register should be made after setting the appropriate AES-
mode and direction. During encryption/ decryption this register can not be accessed.
• Setting START in the Control Register while the State memory and/or Key memory are not
• Accessing (read or write) the Control Register while the START bit is one.
Bit
+0x01
Read/Write
Initial Value
fully loaded or read. This error occurs when the total number of read/write operations from/to
the State and Key register is not a multiple of 16 before an AES Start.
Bit
+0x02
Read/Write
Initial Value
ERROR
R
7
0
R/W
7
0
R
6
0
-
R/W
6
0
R
5
0
-
R/W
5
0
R
4
0
R/W
-
4
0
STATE
R
R/W
3
0
-
3
0
R/W
R
2
0
-
2
0
R/W
R
1
0
-
1
0
XMEGA A
SRIF
R/W
R
0
0
0
0
STATUS
STATE
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