ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 250

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

XMEGA A
When interrupt-driven data reception is used, the receive complete interrupt routine must read
the received data from DATA in order to clear the RXCIF. If not, a new interrupt will occur
directly after the return from the current interrupt. This flag can also be cleared by writing a one
to its bit location.
• Bit 6 - TXCIF: USART Transmit Complete Interrupt Flag
This flag is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data in the transmit buffer (DATA). The TXCIF is automatically cleared when
the transmit complete interrupt vector is executed. The flag can also be cleared by writing a one
to its bit location.
• Bit 5 - DREIF: USART Data Register Empty Flag
The DREIF indicates if the transmit buffer (DATA) is ready to receive new data. The flag is one
when the transmit buffer is empty, and zero when the transmit buffer contains data to be trans-
mitted that has not yet been moved into the Shift Register. DREIF is set after a reset to indicate
that the Transmitter is ready. Always write this bit to zero when writing the STATUS register.
DREIF is cleared by writing DATA. When interrupt-driven data transmission is used, the Data
Register Empty interrupt routine must either write new data to DATA in order to clear DREIF or
disable the Data Register Empty interrupt. If not, a new interrupt will occur directly after the
return from the current interrupt.
• Bit 4 - FERR: Frame Error
The FERR flag indicates the state of the first stop bit of the next readable frame stored in the
receive buffer. The bit is set if the received character had a Frame Error, i.e. when the first stop
bit was zero, and cleared when the stop bit of the received data is one. This bit is valid until the
receive buffer (DATA) is read. The FERR is not affected by setting the SBMODE bit in CTRLC
since the Receiver ignores all, except for the first stop bit. Always write this bit location to zero
when writing the STATUS register.
This flag is not used in Master SPI mode of operation.
• Bit 3 - BUFOVF: Buffer Overflow
The BUFOVF flag indicates data loss due to a receiver buffer full condition. This flag is set if a
Buffer Overflow condition is detected. A Buffer Overflow occurs when the receive buffer is full
(two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is
detected. This flag is valid until the receive buffer (DATA) is read. Always write this bit location to
zero when writing the STATUS register.
This flag is not used in Master SPI mode of operation.
• Bit 2 - PERR: Parity Error
If parity checking is enabled and the next character in the receive buffer has a Parity Error this
flag is set. If Parity Check is not enabled the PERR will always be read as zero. This bit is valid
until the receive buffer (DATA) is read. Always write this bit location to zero when writing the
STATUS register. For details on parity calculation refer to
”Parity Bit Calculation” on page
241.
This flag is not used in Master SPI mode of operation.
• Bit 1 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
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