MT54V512H18E Micron Semiconductor Products, Inc., MT54V512H18E Datasheet - Page 2

• Manufacturer Part Number: MT54V512H18E
• Description: 9Mb QDR SRAM, 2.5V Vdd, HSTL , 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

for each port (read R#, write W#) which are received at
K rising edge. Port selects permit independent port
operation. All synchronous inputs pass through regis-
ters controlled by the K or K# input clock rising edges.
Active LOW byte writes (BW0#, BW1#) permit byte
write selection. Write data and byte writes are regis-
tered on the rising edges of both K and K#. The
addressing within each burst of four is fixed and
sequential. All synchronous data outputs pass through
output registers controlled by the rising edges of the
output clocks (C and C# if provided, otherwise K and
K#).
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed fully-utilized DDR data bus.
sramds) for the latest data sheet.
READ/WRITE Operations
burst of four data, requiring two full clock cycles of bus
utilization. Any request that attempts to interrupt a
NOTE:
512K x 18, 2.5V V
MT54V512H18E_16_A.fm - Rev 10/02
1. The functional block diagram illustrates simplified device operation. See truth tables, ball descriptions, and timing
2. n = 17
D (Data In)
ADDRESS
Depth expansion is accomplished with port selects
Four balls are used to implement JTAG test capabili-
The SRAM operates from a +2.5V power supply, and
Please refer to Micron’s Web site (www.micron.com/
All bus transactions operate on an uninterruptable
diagrams for detailed information.
BW0#
BW1#
W#
R#
K#
DD
K
K
, HSTL, QDRb4 SRAM
W#
R#
18
n
REGISTRY
REGISTRY
ADDRESS
& LOGIC
& LOGIC
DATA
36
36
n
Functional Block Diagram: 512K x 18
K
W
R
T
E
I
G
R
E
W
R
T
E
I
0.16µm Process
D
R
V
R
E
I
Figure 2:
MEMORY
2 x 72
ARRAY
n
2
burst in progress is ignored. The resulting benefit is
that the address rate is kept down to the clock fre-
quency even when both buses are 100 percent utilized.
by asserting R# LOW at K rising edge. Data is delivered
after the next rising edge of K using C and C# as the
output timing references, or using K and K#, if C and
C# are tied HIGH. If C and C# are tied HIGH, they may
not be toggled during device operation. Output tri-
stating is automatically controlled such that the bus is
released if no data is being delivered. This permits
banked SRAM systems with no complex OE timing
generation. Back-to-back READ cycles are initiated
every second K rising edge. Any command in between
is ignored, since the burst sequence may not be inter-
rupted and requires two full clock cycles.
edge. Data is expected at both rising edges of K andK#
beginning one clock period later. Write registers are
incorporated to facilitate pipelined self-timed WRITE
cycles and provide fully coherent data for all combina-
tions of READs and WRITEs. A READ can immediately
follow a WRITE even if they are to the same address.
Although the WRITE data has not been written to the
memory array, the SRAM will deliver the data from the
write register instead of using the older data from the
memory array. The latest data is always utilized for all
bus transactions. WRITE cycles are initiated every sec-
ond K rising edge. Any command in between is
ignored, since the burst sequence may not be inter-
rupted.
READ cycles are pipelined. The request is initiated
WRITE cycles are initiated by W# LOW at K rising
2.5V V
N
Micron Technology, Inc., reserves the right to change products or specifications without notice.
E
E
S
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M
A
P
S
MUX
MUX
DD
36
36
, HSTL, QDRb4 SRAM
C
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T
P
T
G
R
E
C,C#
72
O
U
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P
T
512K x 18
E
E
C
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L
©2002, Micron Technology Inc.
O
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P
T
ADVANCE
U
B
E
R
F
F
18
(Data Out)
Q