MT54V512H18E Micron Semiconductor Products, Inc., MT54V512H18E Datasheet - Page 8

• Manufacturer Part Number: MT54V512H18E
• Description: 9Mb QDR SRAM, 2.5V Vdd, HSTL , 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 4:
Notes 1-8
Table 5:
Note 9
NOTE:
512K x 18, 2.5V V
MT54V512H18E_16_A.fm - Rev 10/02
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. ­ means rising edge; ¯ means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C
3. R# and W# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the ris-
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = /K# = C =/C# when clock is stopped. This is not essential, but permits most rapid restart by
7. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation; however,
8. This signal was HIGH on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecu-
9. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation
OPERATION
OPERATION
WRITE Cycle:
Load address, input write data on
two consecutive K and K# rising
edges
READ Cycle:
Load address, output data on two
consecutive C and C# rising edges
NOP: No operation
STANDBY: Clock stopped
WRITE D0-17 at K rising edge
WRITE D0-17 at K# rising edge
WRITE D0-8 at K rising edge
WRITE D0-8 at K# rising edge
WRITE D9-17 at K rising edge
WRITE D9-17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
and C# are HIGH, then data outputs are delivered at K and K# rising edges.
ing edge of K.
overcoming transmission line charging symmetrically.
it is strongly recommended that this signal is brought HIGH as shown in the Truth Table.
tive K clock rising edges is not permitted. The device will ignore the second request.
provided that the setup and hold requirements are satisfied.
DD
, HSTL, QDRb4 SRAM
Truth Table
BYTE WRITE Operation
Stopped
L®H
L®H
L®H
K
R#
H
L
H
X
8
0.16µm Process
7
W#
L
8
X
H
X
8
Q = High-Z
D
K(t + 1)­
C(t + 1)­
Q
Previous
2.5V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D or Q
A
D = X
State
A
(A + 0)
(A+0)
at
at
L®H
L®H
L®H
L®H
K
DD
Q = High-Z
K#(t + 1)­
C#(t + 1)­
D
Q
Previous
D or Q
A
, HSTL, QDRb4 SRAM
D = X
A
State
(A + 1)
(A+1)
at
at
L®H
L®H
L®H
L®H
K#
Q = High-Z
D
K(t + 2)­
Q
C(t + 2)­
Previous
D or Q
A
D = X
A
State
(A + 2)
(A+2)
at
at
BW0#
512K x 18
0
0
0
0
1
1
1
1
©2002, Micron Technology Inc.
ADVANCE
Q = High-Z
K#(t + 2)­
C#(t + 2)­
D
Q
Previous
D or Q
A
D = X
A
State
BW1#
(A + 3)
(A+3)
at
at
0
0
1
1
0
0
1
1