pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 247

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 9: Registers Description
PNX17XX_SER_1
Preliminary data sheet
Bit
17
16
15
14
13
12
11
10
9
8:7
6
5
4
3
2
1
0
Offset 0x04 0018
31:21
20:0
Offset 0x04 001C
31:21
20:0
Symbol
parking
dis_swapper2targ
dis_swapper2intreg
dis_swapper2dtlinit
regs_wr_post_en
xio_wr_post_en
pci2_wr_post_en
pci1_wr_post_en
en_serr_seen
Reserved
en_base10_spec_rd
en_base14_spec_rd
en_base18_spec_rd
disable_subword2_10
disable_subword2_14
disable_subword2_18
en_retry_timer
pci_base1_lo
Reserved
pci_base1_hi
Reserved
PCI_Base1_lo
PCI_Base1_hi
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
Value
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
Rev. 1 — 17 March 2006
Description
0 = The internal system arbiter will park on the last PCI master to
use the PCI bus.
1 = The internal system arbiter will park on itself.
0 = Enable byte swapping in big endian mode from DCS to PCI
path.
1 = Disable byte swapping in big endian mode from DCS to PCI
path.
0 = Enable byte swapping in big endian mode from PCI to PCI mmio
registers.
1 = Disable byte swapping in big endian mode from PCI to PCI
mmio registers.
0 = Enable byte swapping in big endian mode from PCI to DCS.
1 = Disable byte swapping in big endian mode from PCI to DCS.
Enable write posting to internal PCI registers.
Enable write posting to XIO address range.
Enable write posting to pci_base2 address range.
Enable write posting to pci_base1 address range.
Enable monitoring of the SERR pin.
Read ahead to optimize PCI read latency to base 10.
Read ahead to optimize PCI read latency to base 14.
Read ahead to optimize PCI read latency to base 18.
Disable subword access to/from Base10 aperture.
Disable subword access to/from Base14 aperture.
Disable subword access to/from Base18 aperture.
Enables timer for 16 tic rule enforcer. This bit does not affect access
to the XIO aperture.
For internal address decoding: low bar of first aperture for external
PCI access. This register affects the decode and routing of the bus
controllers. It should not be relied on as stable for 10 clocks after
writing. It is recommended that the PCI_Base1_lo be initialized
before the PCI_Base1_hi to avoid a potentially large segment of
address space being temporarily allocated to PCI space.
For internal address decoding: high bar of first aperture for external
PCI access (up to but not including). This register affects the
decode and routing of the bus controllers. It should not be relied on
as stable for 10 clocks after writing. It is recommended the
PCI_Base1_lo be initialized before the PCI_Base1_hi to avoid a
potentially large segment of address space being temporarily
allocated to PCI space.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
7-26