pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 386

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
3.2.2 Fast Access Registers
Table 6: Shadow Registers
The architecture of the QVCP MMIO access results in module dependent latencies
for the various configuration registers. For most of the registers this does not present
a problem since their content is usually rather static or only updated once per field/
frame. Some registers, however require access with relatively low latency.
lists the QVCP configuration registers which can be accessed with low latency.
Table 7: Fast Access Registers
Register
Output and Alpha manipulation (0x10E[LAPT]B8)
Formats (0x10E[LAPT]BC)
Variable Format Register (0x10E[LAPT]C4)
Start Fetch (0x10E[LAPT]C8)
LSHR_PAR_0 (0x10E[LAPT]E8)
LSHR_PAR_1 (0x10E[LAPT]EC)
LSHR_PAR_2 (0x10E[LAPT]F0)
LSHR_PAR_3 (0x10E[LAPT]F4)
LSHR_E_max (0x10E[LAPT]F8)
LSHR_E_sum (0x10E[LAPT]FC)
LUT-HIST (0x10E[LAPT]124)
LUT-HIST (0x10E[LAPT]128)
LUT-HIST (0x10E[LAPT]12C)
LUT-HIST (0x10E[LAPT]130)
LUT-HIST (0x10E[LAPT]134)
LUT-HIST (0x10E[LAPT]138)
LUT-HIST (0x10E[LAPT]13C)
LUT-HIST (0x10E[LAPT]140)
Layer Histogram control(0x10E[LAPT]144) (enable bit only)
Layer CFTR blue (0x10E[LAPT]48)
Layer CFTR green (0x10E[LAPT]4C)
Layer DCTI control(0x10E[LAPT]50) (enable bit only)
Layer DCTI control(0x10E[LAPT]50) (enable bit only)
Register
Field_Info (0x10 E1F8)
XY_Position (0x10 E1FC)
Interrupt Status (0x10 EFE0)
Interrupt Enable (0x10 EFE4)
Interrupt Clear (0x10 EFE8)
Rev. 1 — 17 March 2006
…Continued
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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PNX17xx Series
Chapter 11: QVCP
Table 7
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