pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 566

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
3. Operation
PNX17XX_SER_1
Preliminary data sheet
3.1.1 SPDIF Input Clock Domains
3.1.2 SPDIF Receiver Sample Rate Tolerance and IEC60958
3.1.3 SPDIF Input Receiver Jitter Tolerance
3.1 Clock Programming
The SPDIF Input module operates using two clock domains. From
SPDIF receiver, decoder and DMA unit use an oversampling clock. The oversampling
clock frequency is software selectable via the chip central clocking function. The
registers blocks use a dtl_mmio clock and resynchronize what’s needed into SPDIF
receiver oversampling clock
The source input stream is oversampled by the SPDIF receiver and a representation
of the bi-phase data bitstream is produced along with a separate internal 64 Fs
bitclock. The oversampling clock used to sample the input stream is a low jitter,
divided form of the system PLL clock. The frequency of the oversampling clock must
be within a certain frequency range described by the following equation
where Fs is the incoming sample rate. Factors affecting this frequency range are
beyond the scope of this document.
To guarantee error free capture for all sample rates, the oversampling frequency
Fosclk must be set to a nominal value. The SPDIF receivers’ internal oversampling
clock frequency can be programmed by selecting a clock divider setting in the central
clock functional block (see
programming details). The divider selections and clocks that are produced are shown
in
Table 1: SPDIF Input Oversampling Clock Value Settings
Three levels of sampling frequency accuracy are specified in the IEC60958
document. The SPDIF receiver will achieve lock onto a level III signal ( variable pitch
shift of +/- 12.5% of Fs ) with respect to all the standard sampling frequencies; 32 kHz,
44.1 kHz and 48 kHz as well as the higher 96 kHz. For this design, the SPDIF
receiver is classified as a level III compliant receiver.
The maximum tolerable input jitter of the SPDIF Input receiver is described by the
equation
1220Fs Fosclk
Tmax jitter
Input Audio Sample
Rate: fs (kHz)
96
32.0, 44.1 and 48.0
Table
1.
=
0.13
2400Fs
Rev. 1 — 17 March 2006
˙
Central PLL Base
Frequency (64x27 MHz)/4
432 MHz
432 MHz
-------------- -
128Fs
.
1
Chapter 5 The Clock Module
Central Clock
Divider n
3
6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
for oversampling clock
PNX17xx Series
Chapter 18: SPDIF Input
Fosclk: Oversampling
Clock freq (MHz)
144.00
72.0
Figure
1, the
(15)
(16)
18-6