pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 356

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 2: LCD CONTROLLER Registers
PNX17XX_SER_1
Preliminary data sheet
Bit
Offset 0x07,3000
Note 1: This is a special register with respect to write.
a software application from altering the delay values after the setup software initialized them correctly. This protects the LCD
panel from being damaged by an incorrect write by a software application.
to the register so that the write-once protection mechanism takes
Note 2:
Note 3: Please refer to Figure 22-2 to correlate the delay values.
31
30
29
28:20
19:16
15:12
11:8
7:4
3:0
Offset 0x07,3004
Note: A board level power sequencing must also be observed to ensure that the LCD panel is powered and ready to accept
the power-up sequence before the power-up sequence is started from PNX17xx Series.
31:1
0
Offset 0x07,3008
31:1
Symbol
The delay values are based on a 27 MHz clock.
LCD_IF_EN
VDD_POL
BKLT_POL
Unused
PWREN_PWREN_DEL
AY
DCE_PWREN_DELAY
BKLT_DCE_DELAY
DCE_BKLT_DELAY
PWREN_DCE_DELAY
Unused
START_PUD_SEQ
Unused
4.1 LCD MMIO Registers
LCD_SETUP
LCD_CNTRL
LCD_STATUS
Acces
s
R/W1
R/W1
R/W1
-
R/W1
R/W1
R/W1
R/W1
R/W1
-
R/W
-
Value
1
1
1
-
11
3
7
2
3
-
0
-
Rev. 1 — 17 March 2006
This is a “write once” register.
Description
This bit enables the LCD interface. If this bit is set, then power
sequencing will be applied to the data/control signals based on the
value of START_PUD_SEQ bit in LCD_CNTRL register. If this bit is
not set, then all the LCD interface signals will remain de-asserted.
When this bit is set, the output router block will select the LCD
interface overriding any other programming of the mux in the output
router.
1 = TFTVDDON is of positive polarity.
0 = TFTVDDON is of negative polarity.
1 = TFTBKLTON is of positive polarity.
0 = TFTBKLTON is of negative polarity.
Delay from the end of a power down sequence to the start of the
next power up sequence. Delay value t6 in steps of 100 ms with 0
corresponding to 100 ms and 15 corresponding to 1600 ms.
Delay from data/control signals de-assertion to the de-assertion of
TFTVDDON signal. Delay value t5 in steps of 10 ms with 0
corresponding to 10 ms and 15 corresponding to 160 ms.
Delay from de-assertion of TFTBKLT signal to the de-assertion of
data/control signals. Delay value t4 in steps of 100 ms with 0
corresponding to 100 ms and 15 corresponding to 1600 ms.
Delay from assertion of data/control signals to TFTBKLT signal
assertion. Delay value t3 in steps of 100 ms with 0 corresponding to
100 ms and 15 corresponding to 1600 ms.
Delay from assertion of TFTVDDON signal to assertion of data/
control signals. Delay value t2 in steps of 10 ms with 0
corresponding to 10 ms and 15 corresponding to 160 ms.
Writing a 1 (when the bit is 0) will start a power up sequencing and
writing a 0 (when the bit is 1) will start a power down sequencing.
When the LCD interface is not enabled, this bit always stays 0.
effect.
Even if default values are desired, do a write
It is implemented this way to prevent
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 10: LCD Controller
PNX17xx Series
10-7