pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 286

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.4.1 GPIO Frequency Restrictions
system memory must have consumed the 64-byte memory before the GPIO logic
needs it again. If the system memory latency is too long then the GPIO logic does not
have an internal 64-byte memory to store in-coming data. In that case GPIO module
generates an internal overrun, INT_OE, interrupt. If pattern generation mode the
Underrun condition is not flagged to the CPU.
If either a FIFO_OE or INT_OE or Underrun error occurs, signal monitoring is
temporarily halted, and incoming timestamps/samples will be lost. In the case of
FIFO_OE, sampling resumes as soon as the control software makes one or more
new buffers available by clearing the relevant BUFx_RDY. In the case of INT_OE, the
GPIO module resumes normal operation as soon as the system memory allows it.
INT_OE and FIFO_OE are ‘sticky’ error flags meaning they will remain set until an
explicit software write of logic ‘1’ to FIFO_OE_CLR or INT_OE_CLR is performed. In
the case of Underrun the GPIO module resumes as soon as data is available.
The GPIO module has two frequency limitations:
One FIFO Enabled
The calculations below show the maximum frequencies allowed for signals to be
monitored and patterns to be generated if only one FIFO queue is enabled and the
minimum latency guarantied by the system is 40 s.
Remark: Sampling calculations assume 1-bit sampling (EN_IO_SEL = 00 or 11).
Timestamping: 1 edge -> 32-bits
=> 16 edges = 64 bytes of data
=> 16 edges can occur every 40 s
=> 1 edge can occur every 2.5 s = 400 kHz maximum frequency.
Sampling: 1 edge -> 1bit
=> 512 edges = 64 bytes of data
=> 512 edges can occur every 40 s
=> 1 edge can occur every 78.125 ns = 12.8 MHz maximum frequency.
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A hardware limitation: the maximum clock used to sample signals or generate
patterns is 108 MHz.
A hardware/software limitation: the system memory latency prevents to fill or
empty the internal 64-byte memories on time. This is not only a hardware
limitation. Indeed the memory latency is dependant on the memory clock speed,
the amount of bandwidth used by the other modules of the PNX17xx Series
system and ultimately by the central internal arbiter settings.
Rev. 1 — 17 March 2006
Chapter 8: General Purpose Input Output Pins
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
8-15