XC2C32 XILINX [Xilinx, Inc], XC2C32 Datasheet - Page 6

• Manufacturer Part Number: XC2C32
• Description: CoolRunner-II CPLD Family
• Manufacturer: XILINX [Xilinx, Inc]

CoolRunner-II CPLD Family
software. The AIM minimizes both propagation delay and
power as it makes attachments to the various FBs.
I/O Block
I/O blocks are primarily transceivers. However, each I/O is
either automatically compliant with standard voltage ranges
or can be programmed to become so. See
detailed information on CoolRunner-II I/Os.
In addition to voltage levels, each input can selectively
arrive through Schmitt-trigger inputs. This adds a small time
delay, but substantially reduces noise on that input pin.
Approximately 500 mV of hysteresis will be added when
Schmitt-trigger inputs are selected. All LVCMOS inputs can
have hysteresis input. Hysteresis also allows easy genera-
tion of external clock circuits. The Schmitt-trigger path is
best seen in
patibility with I/O standards.
Outputs can be directly driven, 3-stated or open-drain con-
figured. A choice of slow or fast slew rate output signal is
Table 5
and shows which standards require V
termination. V
Table 5: CoolRunner-II CPLD I/O Standard Summary
6
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_1
SSTL2_1
SSTL3_1
IOSTANDARD
summarizes the single ended I/O standard support
Attribute
Figure
To Macrocell
REF
Direct Input
detail is given in specific data sheets.
4. See
To AIM
Table 5
V
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
Open Drain
GTS[0:3]
Disabled
Enabled
Figure 4: CoolRunner-II CPLD I/O Block Diagram
for Schmitt-trigger com-
Hysteresis
CGND
REF
CTE
PTB
Input V
values and board
4
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
XAPP382
REF
Available on 128 Macrocell Devices and Larger
From Macrocell
www.xilinx.com
for
Board Termination Voltage
also available.
age standards associated with specific part capacities. All
inputs and disabled outputs are voltage tolerant up to 3.3V.
The CoolRunner-II family supports SSTL2-1, SSTL3-1 and
HSTL-1 high-speed I/O standards in the 128-macrocell and
larger devices.
that the inputs requiring comparison to an external refer-
ence voltage are available. These I/O standards all require
VREF pins for proper operation. The CoolRunner-II CPLD
allows any I/O pin to act as a VREF pin, granting the board
layout engineer extra freedom when laying out the
pins.However, if VREF pin placement is not done properly,
additional VREF pins may be required, resulting in a loss of
potential I/O pins or board re-work. See XAPP399 for
details regarding VREF pins and their placement.
V
The Xilinx software aids designers in remaining within the
proper pin range.
REF
(V
V CCIO
has pin-range requirements that must be observed.
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
TT
)
V REF
Table 5
Figure 4
summarizes various supported volt-
details the I/O pin, where it is noted
Global termination
Pullup/Bus-Hold
Schmitt-trigger Support
DS090 (v2.5) June 28, 2005
Not optional
Not optional
Not optional
Not optional
DS090_04_121201
Optional
Optional
Optional
Optional
Product Specification
R