XC2C32 XILINX [Xilinx, Inc], XC2C32 Datasheet - Page 8

• Manufacturer Part Number: XC2C32
• Description: CoolRunner-II CPLD Family
• Manufacturer: XILINX [Xilinx, Inc]

CoolRunner-II CPLD Family
Global Signals
Global signals, clocks (GCK), sets/resets (GSR) and output
enables (GTS), are designed to strongly resemble each
other. This approach enables design software to make the
best utilization of their capabilities. Each global capability is
supplemented by a corresponding product term version.
Figure 7
trees. The pin input is buffered, then drives multiple internal
global signal traces to deliver low skew and reduce loading
delays. The DataGATE assertion rail is also a global signal.
8
Figure 7: Global Clocks (GCK), Sets/Resets (GSR) and
shows the common structure of the global signal
Output Enables (GTS)
Figure 6: DataGATE Architecture (output drivers not shown)
Latch
Latch
DS090_07_101001
To AIM
To AIM
MC16
MC16
MC1
MC2
MC1
MC2
PLA
PLA
DataGATE Assertion Rail
www.xilinx.com
AIM
Additional Clock Options: Division,
DualEDGE, and CoolCLOCK
Division
Circuitry has been included in the CoolRunner-II CPLD
architecture to divide one externally supplied global clock
by standard values. Division by 2,4,6,8,10, 12, 14 and 16
are the options (see
the GCK2 pin. The resulting clock produced will be 50%
duty cycle for all possible divisions. Note that a Synchro-
nous Reset (CDRST) is included to guarantee no runt
clocks can get through to the global clock nets. Note that
again, the signal is buffered and driven to multiple traces
with minimal loading and skew.
DualEDGE
Each macrocell has the ability to double its input clock
switching frequency.
with the DualEDGE option (doubled clock) at each macro-
cell. The source to double can be a control term clock, a
product term clock or one of the available global clocks. The
ability to switch on both clock edges is vital for a number of
synchronous memory interface applications as well as cer-
tain double data rate I/O applications.
PLA
PLA
MC16
MC16
MC1
MC2
MC1
MC2
To AIM
To AIM
To AIM
Figure
Figure 9
8). This capability is supplied on
Latch
Latch
Latch
shows the macrocell flip-flop
DS090 (v2.5) June 28, 2005
Product Specification
DS090_06_111201
R