XC2C32 XILINX [Xilinx, Inc], XC2C32 Datasheet - Page 12

• Manufacturer Part Number: XC2C32
• Description: CoolRunner-II CPLD Family
• Manufacturer: XILINX [Xilinx, Inc]

CoolRunner-II CPLD Family
device to be programmed at any time. All devices are
shipped in the erased state from the factory.
Applying power to a blank part may result in a higher current
flow as the part initializes. This behavior is normal and may
persist for approximately 2 seconds, depending on the
power supply ramp.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or
boundary-scan tests at any time.
Table 8: I/O Power-Up Characteristics
I/O Banking
CoolRunner-II CPLD XC2C32 and XC2C64 macrocell parts
support a single V
1.5V operation. Two V
XC2C32A, XC2C64A, 128 and 256 macrocell parts where
outputs on each rail can independently range from 3.3V
down to 1.5V operation. Four V
the 384 and 512 macrocell parts. Any of the V
assume any one of the V
3.3V. Designers should assign input and output voltages to
a bank with V
output voltage. The V
Runner-II CPLD must be maintained within 1.8V ±5% for
correct speed operation and proper in system program-
ming.
Mixed Voltage, Power Sequencing, and
Hot Plugging
As mentioned in I/O Banking, CoolRunner-II CPLD parts
support mixed voltage I/O signals. It is important to assign
signals to an I/O bank with the appropriate I/O voltage. Driv-
ing a high voltage into a low voltage bank can result in neg-
ative current flow through the power supply pins. The power
12
IOB Bus-Hold/Weak Pullup
Device Outputs
Device Inputs and Clocks
Function Block
JTAG Controller
Device Circuitry
CCIO
CCIO
set at the voltage range of that input or
CC
rail that can range from 3.3V down to
(internal supply voltage) for a Cool-
CCIO
CCIO
values of 1.5V, 1.8V, 2.5V, or
rails are supported on the
CCIO
Quiescent State
rails are supported on
Weak Pull-up
Disabled
Disabled
Disabled
Disabled
CCIO
rails can
www.xilinx.com
Erased Device Operation
applied to the V
and the CoolRunner-II CPLD will not be damaged. For best
results, we recommend that V
V
the board is inserted into a “live” connector (hot plugged)
and the parts will be well-behaved as if powering up in a
standard way.
Development System Support
Xilinx CoolRunner-II CPLDs are supported by all configura-
tions of Xilinx standard release development software as
well as the freely available ISE WebPACK software avail-
able from www.xilinx.com. Third party development tools
include synthesis tools from Cadence, Exemplar, Mentor
Graphics, Synplicity, and Synopsys.
ATE Support
Third party ATE development support is available for both
programming and board/chip level testing. Vendors provid-
ing this support include Agilent, GenRad, and Teradyne.
Other third party providers are expected to deliver solutions
in the future.
CCINT
3.8 V
(Typ)
1.3V
(Typ)
0V
Weak Pull-up
Figure 12: Device Behavior During Power Up
Power
Disabled
Disabled
Disabled
V
Enabled
. CoolRunner-II CPLDs can reside on boards where
CCINT
No
Quiescent
State
CCIO
and V
Initialization Transition of User Array
User Operation
CC
Bus-Hold/Weak Pullup
Valid User Operation
pins can occur in any order
As Configured
As Configured
As Configured
CCIO
DS090 (v2.5) June 28, 2005
Enabled
Product Specification
be applied before
Quiescent
State
Power
x382_10
No
R