XC2C32 XILINX [Xilinx, Inc], XC2C32 Datasheet - Page 9

• Manufacturer Part Number: XC2C32
• Description: CoolRunner-II CPLD Family
• Manufacturer: XILINX [Xilinx, Inc]

CoolCLOCK
In addition to the DualEDGE flip-flop, additional power sav-
ings can be had by combining the clock division circuitry
with the DualEDGE circuitry. This capability is called Cool-
CLOCK and is designed to reduce clocking power within the
CPLD. Because the clock net can be an appreciable power
DS090 (v2.5) June 28, 2005
Product Specification
R
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
CDRST
Synch Reset
CLK_CT
GCK2
PTC
GCK2
Figure 8: Clock Division Circuitry for GCK2
CTC
PTC
GCK0
GCK1
GCK2
GCK0
GCK1
GCK2
Clock
In
www.xilinx.com
CDRST
Clock
In
Synch Rst
10
12
14
16
2
4
6
8
drain, the clock power can be reduced by driving the net at
half frequency, then doubling the clock rate using
DualEDGE triggering at the macrocells.
how CoolCLOCK is created by internal clock cascading with
the divider and DualEDGE flip-flop working together. See
XAPP378
10
12
14
16
2
4
6
8
PTC
for more detail.
PTC
D/T
CE
CK
D/T
CE
CK
DS090_08_121201
DS090_09_121201
FIF
Latch
DualEDGE
FIF
Latch
DualEDGE
DS090_10_121201
Q
Q
CoolRunner-II CPLD Family
Figure 10
shows
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